[src/trunk]: src/sys/arch/arm/arm Enable branch prediction and write coalesci...

[briggs <briggs%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/2246d23c7e10
branches:  trunk
changeset: 535473:2246d23c7e10
user:      briggs <briggs%NetBSD.org@localhost>
date:      Tue Aug 20 02:00:46 2002 +0000

description:
Enable branch prediction and write coalescing on XScale.

diffstat:

 sys/arch/arm/arm/cpufunc.c |  13 +++++++++++--
 1 files changed, 11 insertions(+), 2 deletions(-)

diffs (40 lines):

diff -r ca7bcbf49eed -r 2246d23c7e10 sys/arch/arm/arm/cpufunc.c
--- a/sys/arch/arm/arm/cpufunc.c        Tue Aug 20 01:52:58 2002 +0000
+++ b/sys/arch/arm/arm/cpufunc.c        Tue Aug 20 02:00:46 2002 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cpufunc.c,v 1.52 2002/08/16 15:25:53 thorpej Exp $     */
+/*     $NetBSD: cpufunc.c,v 1.53 2002/08/20 02:00:46 briggs Exp $      */
 
 /*
  * arm7tdmi support code Copyright (c) 2001 John Fremlin
@@ -1905,6 +1905,7 @@
 xscale_setup(args)
        char *args;
 {
+       uint32_t auxctl;
        int cpuctrl, cpuctrlmask;
 
        /*
@@ -1916,7 +1917,8 @@
        cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
                 | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
                 | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
-                | CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_LABT_ENABLE;
+                | CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_LABT_ENABLE
+                | CPU_CONTROL_BPRD_ENABLE;
        cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
                 | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
                 | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
@@ -1941,5 +1943,12 @@
        curcpu()->ci_ctrl = cpuctrl;
 /*     cpu_control(cpuctrlmask, cpuctrl);*/
        cpu_control(0xffffffff, cpuctrl);
+
+       /* Make sure write coalescing is turned on */
+       __asm __volatile("mrc p15, 0, %0, c1, c0, 1"
+               : "=r" (auxctl));
+       auxctl &= ~XSCALE_AUXCTL_K;
+       __asm __volatile("mcr p15, 0, %0, c1, c0, 1"
+               : : "r" (auxctl));
 }
 #endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 */