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[src/trunk]: src/sys/arch/macppc/macppc add code from tsubai to handle the se...
details: https://anonhg.NetBSD.org/src/rev/29f16ee83a93
branches: trunk
changeset: 534905:29f16ee83a93
user: chs <chs%NetBSD.org@localhost>
date: Tue Aug 06 06:26:19 2002 +0000
description:
add code from tsubai to handle the second CPU on openpic machines.
the second CPU on dual G4 boxes works now.
while I'm here, use mfmsr() and mtmsr() instead of inline asms.
diffstat:
sys/arch/macppc/macppc/cpu.c | 74 +++++++++++++++++++++++++----
sys/arch/macppc/macppc/extintr.c | 98 +++++++++++++++++++++++++--------------
2 files changed, 125 insertions(+), 47 deletions(-)
diffs (truncated from 422 to 300 lines):
diff -r a352b8547f97 -r 29f16ee83a93 sys/arch/macppc/macppc/cpu.c
--- a/sys/arch/macppc/macppc/cpu.c Tue Aug 06 06:21:58 2002 +0000
+++ b/sys/arch/macppc/macppc/cpu.c Tue Aug 06 06:26:19 2002 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.27 2002/07/28 07:06:45 chs Exp $ */
+/* $NetBSD: cpu.c,v 1.28 2002/08/06 06:26:19 chs Exp $ */
/*-
* Copyright (c) 2001 Tsubai Masanari.
@@ -55,6 +55,7 @@
#include <machine/fpu.h>
#include <machine/pcb.h>
#include <machine/pio.h>
+#include <machine/trap.h>
int cpumatch(struct device *, struct cfdata *, void *);
void cpuattach(struct device *, struct device *, void *);
@@ -185,10 +186,14 @@
int i;
struct pcb *pcb;
struct pglist mlist;
+ int pvr, vers;
int error;
int size = 0;
char *cp;
+ pvr = mfpvr();
+ vers = pvr >> 16;
+
/*
* Allocate some contiguous pages for the idle PCB and stack
* from the lowest 256MB (because bat0 always maps it va == pa).
@@ -238,8 +243,34 @@
asm volatile ("sync; isync");
if (openpic_base) {
- /* XXX */
- panic("cpu_spinup");
+ u_int kl_base = 0x80000000; /* XXX */
+ u_int gpio = kl_base + 0x5c; /* XXX */
+ uint64_t tb;
+
+ *(u_int *)EXC_RST = /* ba cpu_spinup_trampoline */
+ 0x48000002 | (u_int)cpu_spinup_trampoline;
+ __syncicache((void *)EXC_RST, 0x100);
+
+ h->running = -1;
+
+ /* Start secondary cpu. */
+ out8(gpio, 4);
+ out8(gpio, 5);
+
+ /* Sync timebase. */
+ tb = mftb();
+ tb += 100000; /* 3ms @ 33MHz */
+
+ h->tbu = tb >> 32;
+ h->tbl = tb & 0xffffffff;
+
+ while (tb > mftb())
+ ;
+
+ asm volatile ("sync; isync");
+ h->running = 0;
+
+ delay(500000);
} else {
/* Start secondary cpu and stop timebase. */
out32(0xf2800000, (int)cpu_spinup_trampoline);
@@ -312,10 +343,15 @@
"mtdbatl 0,%0; mtdbatu 0,%1;"
:: "r"(battable[0].batl), "r"(battable[0].batu));
- /* XXX obio (for now) */
- asm ("mtibatl 1,%0; mtibatu 1,%1;"
- "mtdbatl 1,%0; mtdbatu 1,%1;"
- :: "r"(battable[0xf].batl), "r"(battable[0xf].batu));
+ if (openpic_base) {
+ asm ("mtibatl 1,%0; mtibatu 1,%1;"
+ "mtdbatl 1,%0; mtdbatu 1,%1;"
+ :: "r"(battable[0x8].batl), "r"(battable[0x8].batu));
+ } else {
+ asm ("mtibatl 1,%0; mtibatu 1,%1;"
+ "mtdbatl 1,%0; mtdbatu 1,%1;"
+ :: "r"(battable[0xf].batl), "r"(battable[0xf].batu));
+ }
for (i = 0; i < 16; i++)
asm ("mtsrin %0,%1" :: "r"(h->sr[i]), "r"(i << ADDR_SR_SHFT));
@@ -329,10 +365,24 @@
asm volatile ("mtmsr %0" :: "r"(msr));
asm volatile ("sync; isync");
- h->running = 1;
+
+ if (openpic_base) {
+ /* Sync timebase. */
+ u_int tbu = h->tbu;
+ u_int tbl = h->tbl;
+ while (h->running == -1)
+ ;
+ asm volatile ("sync; isync");
+ asm volatile ("mttbl %0" :: "r"(0));
+ asm volatile ("mttbu %0" :: "r"(tbu));
+ asm volatile ("mttbl %0" :: "r"(tbl));
+ }
cpu_setup(h->self, h->ci);
+ h->running = 1;
+ asm volatile ("sync; isync");
+
while (start_secondary_cpu == 0)
;
@@ -341,7 +391,9 @@
printf("cpu%d: started\n", cpu_number());
asm volatile ("mtdec %0" :: "r"(ticks_per_intr));
- if (!openpic_base)
+ if (openpic_base)
+ openpic_set_priority(cpu_number(), 0);
+ else
out32(HH_INTR_SECONDARY, ~0); /* Reset interrupt. */
curcpu()->ci_ipending = 0;
@@ -365,11 +417,11 @@
{
int cpu_id = ci->ci_cpuid;
- /* printf("send_ipi(%d,%d)\n", cpu_id, mesg); */
+ /* printf("send_ipi(%d, 0x%lx)\n", cpu_id, mesg); */
atomic_setbits_ulong(&IPI[cpu_id], mesg);
if (openpic_base) {
- /* XXX */
+ openpic_write(OPENPIC_IPI(cpu_number(), 1), 1 << cpu_id);
} else {
switch (cpu_id) {
case 0:
diff -r a352b8547f97 -r 29f16ee83a93 sys/arch/macppc/macppc/extintr.c
--- a/sys/arch/macppc/macppc/extintr.c Tue Aug 06 06:21:58 2002 +0000
+++ b/sys/arch/macppc/macppc/extintr.c Tue Aug 06 06:26:19 2002 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: extintr.c,v 1.33 2002/07/05 18:45:17 matt Exp $ */
+/* $NetBSD: extintr.c,v 1.34 2002/08/06 06:26:20 chs Exp $ */
/*-
* Copyright (c) 2000, 2001 Tsubai Masanari.
@@ -94,6 +94,8 @@
volatile int cpl, ipending;
#endif
+#define IPI_VECTOR 64
+
#define interrupt_reg (obio_base + 0x10)
#define INT_STATE_REG_H (interrupt_reg + 0x00)
@@ -349,9 +351,6 @@
return "level-triggered";
default:
panic("intr_typename: invalid type %d", type);
-#if 1 /* XXX */
- return "unknown";
-#endif
}
}
@@ -477,7 +476,6 @@
#ifdef MULTIPROCESSOR
/* Only cpu0 can handle external interrupts. */
if (cpu_number() != 0) {
- /* XXX IPI should be maskable */
out32(HH_INTR_SECONDARY, ~0);
cpuintr(NULL);
return;
@@ -485,13 +483,12 @@
#endif
pcpl = cpl;
- asm volatile ("mfmsr %0" : "=r"(msr));
+ msr = mfmsr();
int_state = gc_read_irq();
#ifdef MULTIPROCESSOR
r_imen = 1 << virq[GC_IPI_IRQ];
if (int_state & r_imen) {
- /* XXX IPI should be maskable */
int_state &= ~r_imen;
cpuintr(NULL);
}
@@ -508,7 +505,7 @@
gc_disable_irq(hwirq[irq]);
} else {
splraise(intrmask[irq]);
- asm volatile ("mtmsr %0" :: "r"(msr | PSL_EE));
+ mtmsr(msr | PSL_EE);
KERNEL_LOCK(LK_CANRECURSE|LK_EXCLUSIVE);
ih = intrhand[irq];
while (ih) {
@@ -516,7 +513,7 @@
ih = ih->ih_next;
}
KERNEL_UNLOCK();
- asm volatile ("mtmsr %0" :: "r"(msr));
+ mtmsr(msr);
cpl = pcpl;
uvmexp.intrs++;
@@ -527,9 +524,9 @@
if (int_state)
goto start;
- asm volatile ("mtmsr %0" :: "r"(msr | PSL_EE));
+ mtmsr(msr | PSL_EE);
splx(pcpl); /* Process pendings. */
- asm volatile ("mtmsr %0" :: "r"(msr));
+ mtmsr(msr);
}
void
@@ -539,14 +536,25 @@
int pcpl, msr, r_imen;
struct intrhand *ih;
+ msr = mfmsr();
+
#ifdef MULTIPROCESSOR
/* Only cpu0 can handle interrupts. */
- if (cpu_number() != 0)
- return;
+ if (cpu_number() != 0) {
+ realirq = openpic_read_irq(cpu_number());
+ while (realirq == IPI_VECTOR) {
+ openpic_eoi(cpu_number());
+ cpuintr(NULL);
+ realirq = openpic_read_irq(cpu_number());
+ }
+ if (realirq == 255) {
+ return;
+ }
+ panic("non-IPI intr %d on cpu%d", realirq, cpu_number());
+ }
#endif
pcpl = cpl;
- asm volatile ("mfmsr %0" : "=r"(msr));
realirq = openpic_read_irq(0);
if (realirq == 255) {
@@ -555,7 +563,19 @@
}
start:
- irq = virq[realirq]; /* XXX check range */
+#ifdef MULTIPROCESSOR
+ while (realirq == IPI_VECTOR) {
+ openpic_eoi(0);
+ cpuintr(NULL);
+
+ realirq = openpic_read_irq(0);
+ if (realirq == 255) {
+ return;
+ }
+ }
+#endif
+ irq = virq[realirq];
+ KASSERT(realirq < ICU_LEN);
r_imen = 1 << irq;
if ((pcpl & r_imen) != 0) {
@@ -563,7 +583,7 @@
openpic_disable_irq(realirq);
} else {
splraise(intrmask[irq]);
- asm volatile ("mtmsr %0" :: "r"(msr | PSL_EE));
+ mtmsr(msr | PSL_EE);
KERNEL_LOCK(LK_CANRECURSE|LK_EXCLUSIVE);
ih = intrhand[irq];
while (ih) {
@@ -571,7 +591,7 @@
ih = ih->ih_next;
}
KERNEL_UNLOCK();
- asm volatile ("mtmsr %0" :: "r"(msr));
+ mtmsr(msr);
cpl = pcpl;
uvmexp.intrs++;
@@ -584,9 +604,9 @@
if (realirq != 255)
goto start;
- asm volatile ("mtmsr %0" :: "r"(msr | PSL_EE));
+ mtmsr(msr | PSL_EE);
splx(pcpl); /* Process pendings. */
- asm volatile ("mtmsr %0" :: "r"(msr));
+ mtmsr(msr);
}
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