Source-Changes-HG archive
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]
[src/trunk]: src/sys/arch/hpcmips/dev You can map mq200 registers as well as ...
details: https://anonhg.NetBSD.org/src/rev/28b5f3455aa9
branches: trunk
changeset: 499665:28b5f3455aa9
user: takemura <takemura%NetBSD.org@localhost>
date: Sun Nov 26 08:33:43 2000 +0000
description:
You can map mq200 registers as well as frame buffer.
(This little change has already contains release 1.5 branch by my mistake)
diffstat:
sys/arch/hpcmips/dev/mq200.c | 13 +-
sys/arch/hpcmips/dev/mq200reg.h | 517 +++++++++++++++++++++++++++++++++++++++-
2 files changed, 521 insertions(+), 9 deletions(-)
diffs (truncated from 576 to 300 lines):
diff -r e63ae1ec945b -r 28b5f3455aa9 sys/arch/hpcmips/dev/mq200.c
--- a/sys/arch/hpcmips/dev/mq200.c Sun Nov 26 06:46:42 2000 +0000
+++ b/sys/arch/hpcmips/dev/mq200.c Sun Nov 26 08:33:43 2000 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: mq200.c,v 1.2 2000/10/02 04:03:06 sato Exp $ */
+/* $NetBSD: mq200.c,v 1.3 2000/11/26 08:33:43 takemura Exp $ */
/*-
* Copyright (c) 2000 Takemura Shin
@@ -135,6 +135,11 @@
sc->sc_dev.dv_xname);
mq200_fbinit(&sc->sc_fbconf);
+ sc->sc_fbconf.hf_baseaddr = MIPS_PHYS_TO_KSEG1(mips_ptob(mips_btop(sc->sc_baseaddr)));
+ sc->sc_fbconf.hf_offset = (u_long)bootinfo->fb_addr -
+ sc->sc_fbconf.hf_baseaddr;
+ DPRINTF(("hf_baseaddr=%lx\n", sc->sc_fbconf.hf_baseaddr));
+ DPRINTF(("hf_offset=%lx\n", sc->sc_fbconf.hf_offset));
if (console && hpcfb_cnattach(&sc->sc_fbconf) != 0) {
panic("mq200_attach: can't init fb console");
@@ -443,10 +448,8 @@
{
struct mq200_softc *sc = (struct mq200_softc *)ctx;
- if (offset < 0 ||
- (sc->sc_fbconf.hf_bytes_per_plane +
- sc->sc_fbconf.hf_offset) < offset)
+ if (offset < 0 || MQ200_MAPSIZE <= offset)
return -1;
- return mips_btop(sc->sc_fbconf.hf_baseaddr + offset);
+ return mips_btop(sc->sc_baseaddr + offset);
}
diff -r e63ae1ec945b -r 28b5f3455aa9 sys/arch/hpcmips/dev/mq200reg.h
--- a/sys/arch/hpcmips/dev/mq200reg.h Sun Nov 26 06:46:42 2000 +0000
+++ b/sys/arch/hpcmips/dev/mq200reg.h Sun Nov 26 08:33:43 2000 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: mq200reg.h,v 1.1 2000/07/22 08:53:36 takemura Exp $ */
+/* $NetBSD: mq200reg.h,v 1.2 2000/11/26 08:33:43 takemura Exp $ */
/*-
* Copyright (c) 2000 Takemura Shin
@@ -31,6 +31,7 @@
#define MQ200_VENDOR_ID 0x4d51
#define MQ200_PRODUCT_ID 0x0200
+#define MQ200_MAPSIZE 0x800000
#define MQ200_POWERSTATE_D0 0
#define MQ200_POWERSTATE_D1 1
@@ -42,13 +43,521 @@
#define MQ200_CC 0x602000 /* CPU interface */
#define MQ200_MM 0x604000 /* memory interface unit */
#define MQ200_IN 0x608000 /* interrupt controller */
-#define MQ200_GC 0x60a000 /* graphice controller */
+#define MQ200_GC(n) (0x60a000+0x80*(n))
+#define MQ200_GC1 0x60a000 /* graphice controller 1*/
+#define MQ200_GC2 0x60a080 /* graphice controller 1*/
#define MQ200_GE 0x60c000 /* graphics engine */
-#define MQ200_FP 0x60e000 /* graphics engine */
+#define MQ200_FP 0x60e000 /* flat panel controller*/
+#define MQ200_CP1 0x610000 /* color palette 1 */
#define MQ200_DC 0x614000 /* device configration */
#define MQ200_PC 0x616000 /* PCI configration */
-/* PCI configuration space */
+/*
+ * Power Management
+ */
+
+/*
+ * CPU Interface
+ */
+
+/*
+ * Memory Interface Unit
+ */
+
+/*
+ * Interrupt Controller
+ */
+
+/*
+ * Graphics Controller 1/2
+ */
+/* GC Control (index: 00h) */
+#define MQ200_GCCR(n) (MQ200_GC(n)+0x00)
+# define MQ200_GCC_ENABLE (1<<0)
+# define MQ200_GCC_HCRESET (1<<1)
+# define MQ200_GCC_VCRESET (1<<2)
+# define MQ200_GCC_EN (1<<3)
+# define MQ200_GCC_DEPTH_SHIFT 4
+# define MQ200_GCC_DEPTH_MASK 0x000000f0
+# define MQ200_GCC_CSREN (1<<8)
+ /* bits 10-9 is reserved */
+# define MQ200_GCC_ALTEN (1<<11)
+# define MQ200_GCC_ALTDEPTH_SHIFT 12
+# define MQ200_GCC_ALTDEPTH_MASK 0x0000f000
+# define MQ200_GCC_RCLK_MASK 0x00030000
+# define MQ200_GCC_RCLK_BUS 0x00000000
+# define MQ200_GCC_RCLK_PLL1 0x00010000
+# define MQ200_GCC_RCLK_PLL2 0x00020000
+# define MQ200_GCC_RCLK_PLL3 0x00030000
+# define MQ200_GCC_TESTMODE0 (1<<18)
+# define MQ200_GCC_TESTMODE1 (1<<19)
+ /* FD(first clock divisor) is 1, 1.5, 2.5, 3.5, 4.5, 5.6 or 6.5 */
+# define MQ200_GCC_MCLK_FD_MASK 0x00700000
+# define MQ200_GCC_MCLK_FD_1 0x00000000
+# define MQ200_GCC_MCLK_FD_1_5 0x00100000
+# define MQ200_GCC_MCLK_FD_2_5 0x00200000
+# define MQ200_GCC_MCLK_FD_3_5 0x00300000
+# define MQ200_GCC_MCLK_FD_4_5 0x00400000
+# define MQ200_GCC_MCLK_FD_5_5 0x00500000
+# define MQ200_GCC_MCLK_FD_6_5 0x00600000
+ /* bit 23 is reserved */
+ /* SD(second close divisor) is 1-255. 0 means disable */
+# define MQ200_GCC_MCLK_SD_SHIFT 24
+# define MQ200_GCC_MCLK_SD_MASK 0xff000000
+ /* GCCR_DEPTH and GCCR_ALTDEPTH values */
+# define MQ200_GCC_1BPP 0x0
+# define MQ200_GCC_2BPP 0x1
+# define MQ200_GCC_4BPP 0x2
+# define MQ200_GCC_8BPP 0x3
+# define MQ200_GCC_16BPP 0x4
+# define MQ200_GCC_24BPP 0x5
+# define MQ200_GCC_ARGB888 0x6
+# define MQ200_GCC_PALBGR 0x6
+# define MQ200_GCC_ABGR888 0x7
+# define MQ200_GCC_PALRGB 0x7
+# define MQ200_GCC_16BPP_DIRECT 0xc
+# define MQ200_GCC_24BPP_DIRECT 0xd
+# define MQ200_GCC_ARGB888_DIRECT 0xe
+# define MQ200_GCC_PALBGR_DIRECT 0xe
+# define MQ200_GCC_ABGR888_DIRECT 0xf
+# define MQ200_GCC_PALRGB_DIRECT 0xf
+
+/* GC CRT Control (index: 04h) */
+#define MQ200_GCCRTCR(n) (MQ200_GC(n)+0x04)
+# define MQ200_GCCRTC_DACEN (1<<0)
+# define MQ200_GCCRTC_HSYNC_PMCLK (1<<2)
+# define MQ200_GCCRTC_VSYNC_PMCLK (1<<3)
+# define MQ200_GCCRTC_HSYNC_LOW 0x00000010
+# define MQ200_GCCRTC_HSYNC_HIGH 0x00000020
+# define MQ200_GCCRTC_VSYNC_LOW 0x00000040
+# define MQ200_GCCRTC_VSYNC_HIGH 0x00000080
+# define MQ200_GCCRTC_HSYNC_ACTVHIGH (0<<8)
+# define MQ200_GCCRTC_HSYNC_ACTVLOW (1<<8)
+# define MQ200_GCCRTC_VSYNC_ACTVHIGH (0<<9)
+# define MQ200_GCCRTC_VSYNC_ACTVLOW (1<<9)
+# define MQ200_GCCRTC_SYNC_PEDESTAL_EN (1<<10)
+# define MQ200_GCCRTC_BLANK_PEDESTAL_EN (1<<11)
+# define MQ200_GCCRTC_COMPOSITE_SYNC_EN (1<<12)
+# define MQ200_GCCRTC_VREF_INTR (0<<13)
+# define MQ200_GCCRTC_VREF_EXTR (1<<13)
+# define MQ200_GCCRTC_MONITOR_SENCE_EN (1<<14)
+# define MQ200_GCCRTC_CONSTAND_OUTPUT_EN (1<<15)
+# define MQ200_GCCRTC_OUTPUT_LEVEL_MASK 0x00ff0000
+# define MQ200_GCCRTC_OUTPUT_LEVEL_SHIFT 16
+# define MQ200_GCCRTC_BLUE_NOTLOADED (1<<24)
+# define MQ200_GCCRTC_RED_NOTLOADED (1<<25)
+# define MQ200_GCCRTC_GREEN_NOTLOADED (1<<26)
+ /* bit 27 is reserved */
+# define MQ200_GCCRTC_COLOR (0<<28)
+# define MQ200_GCCRTC_MONO (1<<28)
+ /* bits 31-29 are reserved */
+
+/* GC Hotizontal Display Control (index: 08h) */
+#define MQ200_GCHDCR(n) (MQ200_GC(n)+0x08)
+# define MQ200_GCHDC_TOTAL_MASK 0x00000fff
+# define MQ200_GCHDC_TOTAL_SHIFT 0
+ /* bits 15-12 are reserved */
+# define MQ200_GCHDC_END_MASK 0x0fff0000
+# define MQ200_GCHDC_END_SHIFT 16
+ /* bits 31-28 are reserved */
+
+/* GC Vertical Display Control (index: 0Ch) */
+#define MQ200_GCVDCR(n) (MQ200_GC(n)+0x0c)
+# define MQ200_GCVDC_TOTAL_MASK 0x00000fff
+# define MQ200_GCVDC_TOTAL_SHIFT 0
+ /* bits 15-12 are reserved */
+# define MQ200_GCVDC_END_MASK 0x0fff0000
+# define MQ200_GCVDC_END_SHIFT 16
+ /* bits 31-28 are reserved */
+
+/* GC Hotizontal Sync Control (index: 10h) */
+#define MQ200_GCHSCR(n) (MQ200_GC(n)+0x10)
+# define MQ200_GCHSC_START_MASK 0x00000fff
+# define MQ200_GCHSC_START_SHIFT 0
+ /* bits 15-12 are reserved */
+# define MQ200_GCHSC_END_MASK 0x0fff0000
+# define MQ200_GCHSC_END_SHIFT 16
+ /* bits 31-28 are reserved */
+
+/* GC Vertical Sync Control (index: 14h) */
+#define MQ200_GCVSCR(n) (MQ200_GC(n)+0x14)
+# define MQ200_GCVSC_START_MASK 0x00000fff
+# define MQ200_GCVSC_START_SHIFT 0
+ /* bits 15-12 are reserved */
+# define MQ200_GCVSC_END_MASK 0x0fff0000
+# define MQ200_GCVSC_END_SHIFT 16
+ /* bits 31-28 are reserved */
+
+/* GC Vertical Display Count (index: 1Ch) */
+#define MQ200_GCVDCNTR(n) (MQ200_GC(n)+0x1c)
+# define MQ200_GCVDCNT_MASK 0x00000fff
+ /* bits 31-12 are reserved */
+
+/* GC Horizontal Window Control (index: 20h) */
+#define MQ200_GCHWCR(n) (MQ200_GC(n)+0x20)
+# define MQ200_GCHWC_START_MASK 0x00000fff
+# define MQ200_GCHWC_START_SHIFT 0
+ /* bits 15-12 are reserved */
+# define MQ200_GCHWC_WIDTH_MASK 0x0fff0000
+# define MQ200_GCHWC_WIDTH_SHIFT 16
+ /* ALD: Additional Line Delta */
+# define MQ200_GCHWC_ALD_MASK 0xf0000000
+# define MQ200_GCHWC_ALD_SHIFT 28
+
+/* GC Vertical Window Control (index: 24h) */
+#define MQ200_GCVWCR(n) (MQ200_GC(n)+0x24)
+# define MQ200_GCVWC_START_MASK 0x00000fff
+# define MQ200_GCVWC_START_SHIFT 0
+ /* bits 15-12 are reserved */
+# define MQ200_GCVWC_HEIGHT_MASK 0x0fff0000
+# define MQ200_GCVWC_HEIGHT_SHIFT 16
+ /* bits 31-28 are reserved */
+
+/* GC Altarnate Horizontal Window Control (index: 28h) */
+#define MQ200_GCHAWCR(n) (MQ200_GC(n)+0x28)
+# define MQ200_GCAHWC_START_MASK 0x00000fff
+# define MQ200_GCAHWC_START_SHIFT 0
+ /* bits 15-12 are reserved */
+# define MQ200_GCAHWC_WIDTH_MASK 0x0fff0000
+# define MQ200_GCAHWC_WIDTH_SHIFT 16
+ /* ALD: Additional Line Delta */
+# define MQ200_GCAHWC_ALD_MASK 0xf0000000
+# define MQ200_GCAHWC_ALD_SHIFT 28
+
+/* GC Alternate Vertical Window Control (index: 2Ch) */
+#define MQ200_GCAVWCR(n) (MQ200_GC(n)+0x2C)
+# define MQ200_GCAVWC_START_MASK 0x00000fff
+# define MQ200_GCAVWC_START_SHIFT 0
+ /* bits 15-12 are reserved */
+# define MQ200_GCAVWC_HEIGHT_MASK 0x0fff0000
+# define MQ200_GCAVWC_HEIGHT_SHIFT 16
+ /* bits 31-28 are reserved */
+
+/* GC Window Start Address (index: 30h) */
+#define MQ200_GCWSAR(n) (MQ200_GC(n)+0x30)
+# define MQ200_GCWSA_MASK 0x000fffff
+ /* bits 31-21 are reserved */
+
+/* GC Alternate Window Start Address (index: 34h) */
+#define MQ200_GCAWSAR(n) (MQ200_GC(n)+0x34)
+# define MQ200_GCAWSA_MASK 0x000fffff
+ /* bits 24-21 are reserved */
+# define MQ200_GCAWPI_MASK 0xfe000000
+# define MQ200_GCAWPI_SHIFT 24 /* XXX, 24 could be usefull
+ than 23 */
+
+/* GC Window Stride (index: 38h) */
+#define MQ200_GCWSTR(n) (MQ200_GC(n)+0x38)
+# define MQ200_GCWST_MASK 0x0000ffff
+# define MQ200_GCWST_SHIFT 0
+# define MQ200_GCWST_ALTMASK 0xffff0000
+# define MQ200_GCWST_ALTSHIFT 16
+
+/* GC Hardware Cursor Position (index: 40h) */
+#define MQ200_GCHCPR(n) (MQ200_GC(n)+0x40)
+# define MQ200_GCHCP_HSTART_MASK 0x00000fff
+# define MQ200_GCHCP_HSTART_SHIFT 0
+ /* bits 15-12 are reserved */
+# define MQ200_GCHCP_VSTART_MASK 0x0fff0000
+# define MQ200_GCHCP_VSTART_SHIFT 16
+ /* bits 31-28 are reserved */
+
+/* GC Hardware Start Address and Offset (index: 44h) */
+#define MQ200_GCHCAOR(n) (MQ200_GC(n)+0x44)
+# define MQ200_GCHCAO_ADDR_MASK 0x00000fff
+# define MQ200_GCHCAO_ADDR_SHIFT 0
+ /* bits 15-12 are reserved */
+# define MQ200_GCHCAO_HOFFSET_MASK 0x003f0000
+# define MQ200_GCHCAO_HOFFSET_SHIFT 16
+ /* bits 23-22 are reserved */
+# define MQ200_GCHCAO_VOFFSET_MASK 0x3f000000
+# define MQ200_GCHCAO_VOFFSET_SHIFT 24
+ /* bits 31-30 are reserved */
+
+/* GC Hardware Cursor Foreground Color (index: 48h) */
+#define MQ200_GCHCFCR(n) (MQ200_GC(n)+0x48)
+# define MQ200_GCHCFC_MASK 0x00ffffff
+ /* you can use MQ200_GC_RGB macro */
+ /* bits 31-24 are reserved */
+
+/* GC Hardware Cursor Background Color (index: 4Ch) */
+#define MQ200_GCHCBCR(n) (MQ200_GC(n)+0x4c)
+# define MQ200_GCHCBC_MASK 0x00ffffff
+ /* you can use MQ200_GC_RGB macro */
+ /* bits 31-24 are reserved */
Home |
Main Index |
Thread Index |
Old Index