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[src/trunk]: src/sys/arch Add a new option EVBARM_BOARDTYPE to differentiate ...
details: https://anonhg.NetBSD.org/src/rev/b24f84597d2f
branches: trunk
changeset: 535399:b24f84597d2f
user: briggs <briggs%NetBSD.org@localhost>
date: Sat Aug 17 16:42:20 2002 +0000
description:
Add a new option EVBARM_BOARDTYPE to differentiate between different
evbarm ports. Inline _splraise/_spllower/splx for i80321 and iq80310
for more performance.
diffstat:
sys/arch/arm/xscale/i80321_icu.c | 126 ++++++++++++++++++------------
sys/arch/arm/xscale/i80321_intr.h | 124 +++++++++++++++++++++++++++++
sys/arch/evbarm/conf/IQ80321 | 7 +-
sys/arch/evbarm/conf/TEAMASA_NPWR | 6 +-
sys/arch/evbarm/conf/files.evbarm | 3 +-
sys/arch/evbarm/conf/std.integrator | 6 +-
sys/arch/evbarm/conf/std.iq80310 | 4 +-
sys/arch/evbarm/conf/std.iq80321 | 4 +-
sys/arch/evbarm/conf/std.ixm1200 | 4 +-
sys/arch/evbarm/include/cpu.h | 13 ++-
sys/arch/evbarm/include/intr.h | 66 ++++++++++++++-
sys/arch/evbarm/iq80310/iq80310_intr.c | 117 ++++++++++++++-------------
sys/arch/evbarm/iq80310/iq80310_intr.h | 137 +++++++++++++++++++++++++++++++++
sys/arch/evbarm/ixm1200/ixm1200_intr.h | 46 +++++++++++
14 files changed, 542 insertions(+), 121 deletions(-)
diffs (truncated from 1154 to 300 lines):
diff -r 4eeec30c7d91 -r b24f84597d2f sys/arch/arm/xscale/i80321_icu.c
--- a/sys/arch/arm/xscale/i80321_icu.c Sat Aug 17 16:36:31 2002 +0000
+++ b/sys/arch/arm/xscale/i80321_icu.c Sat Aug 17 16:42:20 2002 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: i80321_icu.c,v 1.4 2002/08/14 19:47:18 thorpej Exp $ */
+/* $NetBSD: i80321_icu.c,v 1.5 2002/08/17 16:42:20 briggs Exp $ */
/*
* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
@@ -57,13 +57,13 @@
struct intrq intrq[NIRQ];
/* Interrupts to mask at each level. */
-static int imask[NIPL];
+int i80321_imask[NIPL];
/* Current interrupt priority level. */
__volatile int current_spl_level;
/* Interrupts pending. */
-static __volatile int ipending;
+__volatile int i80321_ipending;
/* Software copy of the IRQs we have enabled. */
__volatile uint32_t intr_enabled;
@@ -155,14 +155,17 @@
return (iintsrc & intr_enabled);
}
+#if defined(EVBARM_SPL_NOINLINE)
static __inline void
i80321_set_intrmask(void)
{
+ extern __volatile uint32_t intr_enabled;
__asm __volatile("mcr p6, 0, %0, c0, c0, 0"
:
: "r" (intr_enabled & ICU_INT_HWMASK));
}
+#endif
static __inline void
i80321_set_intrsteer(void)
@@ -217,76 +220,76 @@
if (intrq[irq].iq_levels & (1U << ipl))
irqs |= (1U << irq);
}
- imask[ipl] = irqs;
+ i80321_imask[ipl] = irqs;
}
- imask[IPL_NONE] = 0;
+ i80321_imask[IPL_NONE] = 0;
/*
* Initialize the soft interrupt masks to block themselves.
*/
- imask[IPL_SOFT] = SI_TO_IRQBIT(SI_SOFT);
- imask[IPL_SOFTCLOCK] = SI_TO_IRQBIT(SI_SOFTCLOCK);
- imask[IPL_SOFTNET] = SI_TO_IRQBIT(SI_SOFTNET);
- imask[IPL_SOFTSERIAL] = SI_TO_IRQBIT(SI_SOFTSERIAL);
+ i80321_imask[IPL_SOFT] = SI_TO_IRQBIT(SI_SOFT);
+ i80321_imask[IPL_SOFTCLOCK] = SI_TO_IRQBIT(SI_SOFTCLOCK);
+ i80321_imask[IPL_SOFTNET] = SI_TO_IRQBIT(SI_SOFTNET);
+ i80321_imask[IPL_SOFTSERIAL] = SI_TO_IRQBIT(SI_SOFTSERIAL);
/*
* splsoftclock() is the only interface that users of the
* generic software interrupt facility have to block their
* soft intrs, so splsoftclock() must also block IPL_SOFT.
*/
- imask[IPL_SOFTCLOCK] |= imask[IPL_SOFT];
+ i80321_imask[IPL_SOFTCLOCK] |= i80321_imask[IPL_SOFT];
/*
* splsoftnet() must also block splsoftclock(), since we don't
* want timer-driven network events to occur while we're
* processing incoming packets.
*/
- imask[IPL_SOFTNET] |= imask[IPL_SOFTCLOCK];
+ i80321_imask[IPL_SOFTNET] |= i80321_imask[IPL_SOFTCLOCK];
/*
* Enforce a heirarchy that gives "slow" device (or devices with
* limited input buffer space/"real-time" requirements) a better
* chance at not dropping data.
*/
- imask[IPL_BIO] |= imask[IPL_SOFTNET];
- imask[IPL_NET] |= imask[IPL_BIO];
- imask[IPL_SOFTSERIAL] |= imask[IPL_NET];
- imask[IPL_TTY] |= imask[IPL_SOFTSERIAL];
+ i80321_imask[IPL_BIO] |= i80321_imask[IPL_SOFTNET];
+ i80321_imask[IPL_NET] |= i80321_imask[IPL_BIO];
+ i80321_imask[IPL_SOFTSERIAL] |= i80321_imask[IPL_NET];
+ i80321_imask[IPL_TTY] |= i80321_imask[IPL_SOFTSERIAL];
/*
* splvm() blocks all interrupts that use the kernel memory
* allocation facilities.
*/
- imask[IPL_IMP] |= imask[IPL_TTY];
+ i80321_imask[IPL_IMP] |= i80321_imask[IPL_TTY];
/*
* Audio devices are not allowed to perform memory allocation
* in their interrupt routines, and they have fairly "real-time"
* requirements, so give them a high interrupt priority.
*/
- imask[IPL_AUDIO] |= imask[IPL_IMP];
+ i80321_imask[IPL_AUDIO] |= i80321_imask[IPL_IMP];
/*
* splclock() must block anything that uses the scheduler.
*/
- imask[IPL_CLOCK] |= imask[IPL_AUDIO];
+ i80321_imask[IPL_CLOCK] |= i80321_imask[IPL_AUDIO];
/*
* No separate statclock on the IQ80310.
*/
- imask[IPL_STATCLOCK] |= imask[IPL_CLOCK];
+ i80321_imask[IPL_STATCLOCK] |= i80321_imask[IPL_CLOCK];
/*
* splhigh() must block "everything".
*/
- imask[IPL_HIGH] |= imask[IPL_STATCLOCK];
+ i80321_imask[IPL_HIGH] |= i80321_imask[IPL_STATCLOCK];
/*
* XXX We need serial drivers to run at the absolute highest priority
* in order to avoid overruns, so serial > high.
*/
- imask[IPL_SERIAL] |= imask[IPL_HIGH];
+ i80321_imask[IPL_SERIAL] |= i80321_imask[IPL_HIGH];
/*
* Now compute which IRQs must be blocked when servicing any
@@ -299,12 +302,12 @@
i80321_enable_irq(irq);
for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL;
ih = TAILQ_NEXT(ih, ih_list))
- irqs |= imask[ih->ih_ipl];
+ irqs |= i80321_imask[ih->ih_ipl];
iq->iq_mask = irqs;
}
}
-static void
+__inline void
i80321_do_pending(void)
{
static __cpu_simple_lock_t processing = __SIMPLELOCK_UNLOCKED;
@@ -318,9 +321,9 @@
oldirqstate = disable_interrupts(I32_bit);
#define DO_SOFTINT(si) \
- if ((ipending & ~new) & SI_TO_IRQBIT(si)) { \
- ipending &= ~SI_TO_IRQBIT(si); \
- current_spl_level |= imask[si_to_ipl[(si)]]; \
+ if ((i80321_ipending & ~new) & SI_TO_IRQBIT(si)) { \
+ i80321_ipending &= ~SI_TO_IRQBIT(si); \
+ current_spl_level |= i80321_imask[si_to_ipl[(si)]]; \
restore_interrupts(oldirqstate); \
softintr_dispatch(si); \
oldirqstate = disable_interrupts(I32_bit); \
@@ -337,16 +340,7 @@
restore_interrupts(oldirqstate);
}
-int
-_splraise(int ipl)
-{
- int old;
-
- old = current_spl_level;
- current_spl_level |= imask[ipl];
-
- return (old);
-}
+#if defined(EVBARM_SPL_NOINLINE)
__inline void
splx(int new)
@@ -355,12 +349,7 @@
current_spl_level = new;
- /*
- * If there are pending HW interrupts which are being
- * unmasked, then enable them in the INTCTL register.
- * This will cause them to come flooding in.
- */
- hwpend = (ipending & ICU_INT_HWMASK) & ~new;
+ hwpend = (i80321_ipending & ICU_INT_HWMASK) & ~new;
if (hwpend != 0) {
oldirqstate = disable_interrupts(I32_bit);
intr_enabled |= hwpend;
@@ -368,31 +357,66 @@
restore_interrupts(oldirqstate);
}
- /* If there are software interrupts to process, do it. */
- if ((ipending & INT_SWMASK) & ~new)
+ if ((i80321_ipending & INT_SWMASK) & ~new)
i80321_do_pending();
}
int
+_splraise(int ipl)
+{
+ int old;
+
+ old = current_spl_level;
+ current_spl_level |= i80321_imask[ipl];
+
+ return (old);
+}
+
+int
_spllower(int ipl)
{
int old = current_spl_level;
- splx(imask[ipl]);
- return (old);
+ splx(i80321_imask[ipl]);
+ return(old);
+}
+
+#else /* EVBARM_SPL_NOINLINE */
+
+#undef splx
+__inline void
+splx(int new)
+{
+ i80321_splx(new);
}
+#undef _spllower
+int
+_spllower(int ipl)
+{
+ return i80321_spllower(ipl);
+}
+
+#undef _splraise
+int
+_splraise(int ipl)
+{
+ return i80321_splraise(ipl);
+}
+
+#endif /* else EVBARM_SPL_NOINLINE */
+
void
_setsoftintr(int si)
{
int oldirqstate;
oldirqstate = disable_interrupts(I32_bit);
- ipending |= SI_TO_IRQBIT(si);
+ i80321_ipending |= SI_TO_IRQBIT(si);
restore_interrupts(oldirqstate);
/* Process unmasked pending soft interrupts. */
- if ((ipending & INT_SWMASK) & ~current_spl_level)
+ if ((i80321_ipending & INT_SWMASK) & ~current_spl_level)
i80321_do_pending();
}
@@ -521,11 +545,11 @@
* IRQ is masked; mark it as pending and check
* the next one. Note: the IRQ is already disabled.
*/
- ipending |= ibit;
+ i80321_ipending |= ibit;
continue;
}
- ipending &= ~ibit;
+ i80321_ipending &= ~ibit;
iq = &intrq[irq];
iq->iq_ev.ev_count++;
@@ -546,7 +570,7 @@
}
/* Check for pendings soft intrs. */
- if ((ipending & INT_SWMASK) & ~current_spl_level) {
+ if ((i80321_ipending & INT_SWMASK) & ~current_spl_level) {
oldirqstate = enable_interrupts(I32_bit);
i80321_do_pending();
restore_interrupts(oldirqstate);
diff -r 4eeec30c7d91 -r b24f84597d2f sys/arch/arm/xscale/i80321_intr.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/xscale/i80321_intr.h Sat Aug 17 16:42:20 2002 +0000
@@ -0,0 +1,124 @@
+/* $NetBSD: i80321_intr.h,v 1.1 2002/08/17 16:42:20 briggs Exp $ */
+
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