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[src/trunk]: src/sys/arch/i386 No need for two copies of the i8253 register d...
details: https://anonhg.NetBSD.org/src/rev/4ca1d4481baa
branches: trunk
changeset: 535253:4ca1d4481baa
user: thorpej <thorpej%NetBSD.org@localhost>
date: Tue Aug 13 00:50:33 2002 +0000
description:
No need for two copies of the i8253 register definitions. Remove the
i386-specific copy, and adjust its users to add in the timer i/o base
as necessary.
diffstat:
sys/arch/i386/i386/microtime.s | 12 ++--
sys/arch/i386/isa/clock.c | 30 ++++++------
sys/arch/i386/isa/timerreg.h | 100 -----------------------------------------
3 files changed, 21 insertions(+), 121 deletions(-)
diffs (216 lines):
diff -r 3725587b3b27 -r 4ca1d4481baa sys/arch/i386/i386/microtime.s
--- a/sys/arch/i386/i386/microtime.s Mon Aug 12 22:44:03 2002 +0000
+++ b/sys/arch/i386/i386/microtime.s Tue Aug 13 00:50:33 2002 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: microtime.s,v 1.20 2001/07/17 13:52:24 mrg Exp $ */
+/* $NetBSD: microtime.s,v 1.21 2002/08/13 00:50:33 thorpej Exp $ */
/*-
* Copyright (c) 1993 The Regents of the University of California.
@@ -35,7 +35,7 @@
#include <machine/asm.h>
#include <dev/isa/isareg.h>
-#include <i386/isa/timerreg.h>
+#include <dev/ic/i8253reg.h>
/* LINTSTUB: include <sys/time.h> */
@@ -53,14 +53,14 @@
cli # disable interrupts
# select timer 0 and latch its counter
- outb %al,$TIMER_MODE
+ outb %al,$IO_TIMER1+TIMER_MODE
inb $IO_ICU1,%al # as close to timer latch as possible
movb %al,%ch # %ch is current ICU mask
# Read counter value into [%al %dl], LSB first
- inb $TIMER_CNTR0,%al
- movb %al,%dl # %dl has LSB
- inb $TIMER_CNTR0,%al # %al has MSB
+ inb $IO_TIMER1+TIMER_CNTR0,%al
+ movb %al,%dl # %dl has LSB
+ inb $IO_TIMER1+TIMER_CNTR0,%al # %al has MSB
# save state of IIR in ICU, and of ipending, for later perusal
movb _C_LABEL(ipending) + IRQ_BYTE(0),%cl # %cl is interrupt pending
diff -r 3725587b3b27 -r 4ca1d4481baa sys/arch/i386/isa/clock.c
--- a/sys/arch/i386/isa/clock.c Mon Aug 12 22:44:03 2002 +0000
+++ b/sys/arch/i386/isa/clock.c Tue Aug 13 00:50:33 2002 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: clock.c,v 1.70 2002/01/01 09:14:14 perry Exp $ */
+/* $NetBSD: clock.c,v 1.71 2002/08/13 00:50:34 thorpej Exp $ */
/*-
* Copyright (c) 1993, 1994 Charles M. Hannum.
@@ -90,7 +90,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: clock.c,v 1.70 2002/01/01 09:14:14 perry Exp $");
+__KERNEL_RCSID(0, "$NetBSD: clock.c,v 1.71 2002/08/13 00:50:34 thorpej Exp $");
/* #define CLOCKDEBUG */
/* #define CLOCK_PARANOIA */
@@ -109,8 +109,8 @@
#include <dev/isa/isareg.h>
#include <dev/isa/isavar.h>
#include <dev/ic/mc146818reg.h>
+#include <dev/ic/i8253reg.h>
#include <i386/isa/nvram.h>
-#include <i386/isa/timerreg.h>
#include <dev/clock_subr.h>
#include "mca.h"
@@ -219,12 +219,12 @@
ef = read_eflags();
disable_intr();
- v1 = inb(TIMER_CNTR0);
- v1 |= inb(TIMER_CNTR0) << 8;
- v2 = inb(TIMER_CNTR0);
- v2 |= inb(TIMER_CNTR0) << 8;
- v3 = inb(TIMER_CNTR0);
- v3 |= inb(TIMER_CNTR0) << 8;
+ v1 = inb(IO_TIMER1+TIMER_CNTR0);
+ v1 |= inb(IO_TIMER1+TIMER_CNTR0) << 8;
+ v2 = inb(IO_TIMER1+TIMER_CNTR0);
+ v2 |= inb(IO_TIMER1+TIMER_CNTR0) << 8;
+ v3 = inb(IO_TIMER1+TIMER_CNTR0);
+ v3 |= inb(IO_TIMER1+TIMER_CNTR0) << 8;
write_eflags(ef);
@@ -293,11 +293,11 @@
tval = (tval / 2) + (tval & 0x1);
/* initialize 8253 clock */
- outb(TIMER_MODE, TIMER_SEL0|TIMER_RATEGEN|TIMER_16BIT);
+ outb(IO_TIMER1+TIMER_MODE, TIMER_SEL0|TIMER_RATEGEN|TIMER_16BIT);
/* Correct rounding will buy us a better precision in timekeeping */
- outb(IO_TIMER1, tval % 256);
- outb(IO_TIMER1, tval / 256);
+ outb(IO_TIMER1+TIMER_CNTR0, tval % 256);
+ outb(IO_TIMER1+TIMER_CNTR0, tval / 256);
rtclock_tval = tval;
@@ -434,9 +434,9 @@
ef = read_eflags();
disable_intr();
/* Select counter 0 and latch it. */
- outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
- lo = inb(TIMER_CNTR0);
- hi = inb(TIMER_CNTR0);
+ outb(IO_TIMER1+TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
+ lo = inb(IO_TIMER1+TIMER_CNTR0);
+ hi = inb(IO_TIMER1+TIMER_CNTR0);
write_eflags(ef);
return ((hi << 8) | lo);
}
diff -r 3725587b3b27 -r 4ca1d4481baa sys/arch/i386/isa/timerreg.h
--- a/sys/arch/i386/isa/timerreg.h Mon Aug 12 22:44:03 2002 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,100 +0,0 @@
-/* $NetBSD: timerreg.h,v 1.4 1994/10/27 04:18:17 cgd Exp $ */
-
-/*-
- * Copyright (c) 1993 The Regents of the University of California.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- * must display the following acknowledgement:
- * This product includes software developed by the University of
- * California, Berkeley and its contributors.
- * 4. Neither the name of the University nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-/*
- * Register definitions for the Intel 8253 Programmable Interval Timer.
- *
- * This chip has three independent 16-bit down counters that can be
- * read on the fly. There are three mode registers and three countdown
- * registers. The countdown registers are addressed directly, via the
- * first three I/O ports. The three mode registers are accessed via
- * the fourth I/O port, with two bits in the mode byte indicating the
- * register. (Why are hardware interfaces always so braindead?).
- *
- * To write a value into the countdown register, the mode register
- * is first programmed with a command indicating the which byte of
- * the two byte register is to be modified. The three possibilities
- * are load msb (TMR_MR_MSB), load lsb (TMR_MR_LSB), or load lsb then
- * msb (TMR_MR_BOTH).
- *
- * To read the current value ("on the fly") from the countdown register,
- * you write a "latch" command into the mode register, then read the stable
- * value from the corresponding I/O port. For example, you write
- * TMR_MR_LATCH into the corresponding mode register. Presumably,
- * after doing this, a write operation to the I/O port would result
- * in undefined behavior (but hopefully not fry the chip).
- * Reading in this manner has no side effects.
- *
- * The outputs of the three timers are connected as follows:
- *
- * timer 0 -> irq 0
- * timer 1 -> dma chan 0 (for dram refresh)
- * timer 2 -> speaker (via keyboard controller)
- *
- * Timer 0 is used to call hardclock.
- * Timer 2 is used to generate console beeps.
- */
-
-/*
- * Frequency of all three count-down timers; (TIMER_FREQ/freq) is the
- * appropriate count to generate a frequency of freq hz.
- */
-#ifndef TIMER_FREQ
-#define TIMER_FREQ 1193182
-#endif
-#define TIMER_DIV(x) ((TIMER_FREQ+(x)/2)/(x))
-
-/*
- * Macros for specifying values to be written into a mode register.
- */
-#define TIMER_CNTR0 (IO_TIMER1 + 0) /* timer 0 counter port */
-#define TIMER_CNTR1 (IO_TIMER1 + 1) /* timer 1 counter port */
-#define TIMER_CNTR2 (IO_TIMER1 + 2) /* timer 2 counter port */
-#define TIMER_MODE (IO_TIMER1 + 3) /* timer mode port */
-#define TIMER_SEL0 0x00 /* select counter 0 */
-#define TIMER_SEL1 0x40 /* select counter 1 */
-#define TIMER_SEL2 0x80 /* select counter 2 */
-#define TIMER_INTTC 0x00 /* mode 0, intr on terminal cnt */
-#define TIMER_ONESHOT 0x02 /* mode 1, one shot */
-#define TIMER_RATEGEN 0x04 /* mode 2, rate generator */
-#define TIMER_SQWAVE 0x06 /* mode 3, square wave */
-#define TIMER_SWSTROBE 0x08 /* mode 4, s/w triggered strobe */
-#define TIMER_HWSTROBE 0x0a /* mode 5, h/w triggered strobe */
-#define TIMER_LATCH 0x00 /* latch counter for reading */
-#define TIMER_LSB 0x10 /* r/w counter LSB */
-#define TIMER_MSB 0x20 /* r/w counter MSB */
-#define TIMER_16BIT 0x30 /* r/w counter 16 bits, LSB first */
-#define TIMER_BCD 0x01 /* count in BCD */
-
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