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[src/trunk]: src/sys/arch/sparc/sparc Use C-style comments in a few places wh...
details: https://anonhg.NetBSD.org/src/rev/f48c8a147e0a
branches: trunk
changeset: 532126:f48c8a147e0a
user: thorpej <thorpej%NetBSD.org@localhost>
date: Fri May 31 19:59:00 2002 +0000
description:
Use C-style comments in a few places where ' appears in the comment,
so that this works with GCC 2.95.3's ISO C preprocessor.
diffstat:
sys/arch/sparc/sparc/bsd_fdintr.s | 10 ++++++----
sys/arch/sparc/sparc/locore.s | 12 ++++++------
2 files changed, 12 insertions(+), 10 deletions(-)
diffs (78 lines):
diff -r c023e1553647 -r f48c8a147e0a sys/arch/sparc/sparc/bsd_fdintr.s
--- a/sys/arch/sparc/sparc/bsd_fdintr.s Fri May 31 19:49:42 2002 +0000
+++ b/sys/arch/sparc/sparc/bsd_fdintr.s Fri May 31 19:59:00 2002 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: bsd_fdintr.s,v 1.19 2001/03/15 03:01:40 mrg Exp $ */
+/* $NetBSD: bsd_fdintr.s,v 1.20 2002/05/31 19:59:00 thorpej Exp $ */
/*
* Copyright (c) 1995 Paul Kranenburg
@@ -182,9 +182,11 @@
inc %l6
st %l6, [R_fdc + FDC_EVCNT]
- ! load chips register addresses
- ! NOTE: we ignore the bus tag here and assume the bus handle
- ! is the virtual address of the chip's registers.
+ /*
+ * load chips register addresses
+ * NOTE: we ignore the bus tag here and assume the bus handle
+ * is the virtual address of the chip's registers.
+ */
ld [R_fdc + FDC_REG_HANDLE], %l7 ! get chip registers bus handle
ld [R_fdc + FDC_REG_MSR], R_msr ! get chip MSR reg addr
add R_msr, %l7, R_msr
diff -r c023e1553647 -r f48c8a147e0a sys/arch/sparc/sparc/locore.s
--- a/sys/arch/sparc/sparc/locore.s Fri May 31 19:49:42 2002 +0000
+++ b/sys/arch/sparc/sparc/locore.s Fri May 31 19:59:00 2002 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.s,v 1.153 2002/02/04 08:36:36 pk Exp $ */
+/* $NetBSD: locore.s,v 1.154 2002/05/31 19:59:00 thorpej Exp $ */
/*
* Copyright (c) 1996 Paul Kranenburg
@@ -1686,7 +1686,7 @@
bl,a ctw_merge ! all ok if only 1
std %l0, [%sp]
add %sp, 7*8, %g5 ! check last addr too
- add %g6, 62, %g6 ! restore %g6 to `pgofset'
+ add %g6, 62, %g6 /* restore %g6 to `pgofset' */
PTE_OF_ADDR(%g5, %g7, ctw_invalid, %g6, NOP_ON_4M_3)
CMP_PTE_USER_WRITE(%g7, %g6, NOP_ON_4M_4)
be,a ctw_merge ! all ok: store <l0,l1> and merge
@@ -2700,7 +2700,7 @@
bnz,a 1f !
mov %o0, %o1 ! shift int clear bit to SOFTINT 15
- set _C_LABEL(nmi_hard), %o3 ! it's a hardint; switch handler
+ set _C_LABEL(nmi_hard), %o3 /* it's a hardint; switch handler */
/*
* Level 15 interrupts are nonmaskable, so with traps off,
@@ -2767,7 +2767,7 @@
!cmp %o0, 0 ! was this a soft nmi
!be 4f
- !XXX - we need to unblock `mask all ints' only on a hard nmi
+ /* XXX - we need to unblock `mask all ints' only on a hard nmi */
! enable interrupts again (safe, we disabled traps again above)
sethi %hi(ICR_SI_CLR), %o0
@@ -3461,7 +3461,7 @@
set 0x44444230, %l3 ! Is it DDB_MAGIC0?
cmp %o5, %l3 ! if so, need to relocate %o4
- bne 3f ! if not, there's no bootloader info
+ bne 3f /* if not, there's no bootloader info */
! note: %l4 set to KERNBASE above.
set 0xf8000000, %l5 ! compute correction term:
@@ -4499,7 +4499,7 @@
#if defined(MULTIPROCESSOR) || defined(LOCKDEBUG)
idle_leave:
/* Before we leave the idle loop, detain the scheduler lock */
- nop;nop;nop; ! just wrote to %psr; delay before doing a `save'
+ nop;nop;nop; /* just wrote to %psr; delay before doing a `save' */
SAVE_GLOBALS_AND_CALL(sched_lock_idle)
b,a Lsw_scan
#endif
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