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[src/trunk]: src/sys/arch/arm add support for ixp12x0
details: https://anonhg.NetBSD.org/src/rev/07ef7e415693
branches: trunk
changeset: 534080:07ef7e415693
user: ichiro <ichiro%NetBSD.org@localhost>
date: Mon Jul 15 16:27:15 2002 +0000
description:
add support for ixp12x0
diffstat:
sys/arch/arm/arm/cpufunc.c | 115 ++++-
sys/arch/arm/arm/cpufunc_asm_ixp12x0.S | 89 +++
sys/arch/arm/conf/files.arm | 9 +-
sys/arch/arm/include/cpuconf.h | 8 +-
sys/arch/arm/include/cpufunc.h | 8 +-
sys/arch/arm/ixp12x0/files.ixp12x0 | 31 +
sys/arch/arm/ixp12x0/ixp12x0.c | 260 ++++++++++
sys/arch/arm/ixp12x0/ixp12x0_clk.c | 388 +++++++++++++++
sys/arch/arm/ixp12x0/ixp12x0_clkreg.h | 125 ++++
sys/arch/arm/ixp12x0/ixp12x0_com.c | 836 +++++++++++++++++++++++++++++++++
sys/arch/arm/ixp12x0/ixp12x0_com_io.c | 202 +++++++
sys/arch/arm/ixp12x0/ixp12x0_comreg.h | 94 +++
sys/arch/arm/ixp12x0/ixp12x0_comvar.h | 102 ++++
sys/arch/arm/ixp12x0/ixp12x0_intr.c | 569 ++++++++++++++++++++++
sys/arch/arm/ixp12x0/ixp12x0_io.c | 382 +++++++++++++++
sys/arch/arm/ixp12x0/ixp12x0_irq.S | 155 ++++++
sys/arch/arm/ixp12x0/ixp12x0_pci.c | 193 +++++++
sys/arch/arm/ixp12x0/ixp12x0_pci_dma.c | 66 ++
sys/arch/arm/ixp12x0/ixp12x0_pcireg.h | 195 +++++++
sys/arch/arm/ixp12x0/ixp12x0reg.h | 265 ++++++++++
sys/arch/arm/ixp12x0/ixp12x0var.h | 111 ++++
sys/arch/arm/ixp12x0/ixpsip.c | 117 ++++
sys/arch/arm/ixp12x0/ixpsip_io.c | 230 +++++++++
sys/arch/arm/ixp12x0/ixpsipvar.h | 57 ++
24 files changed, 4597 insertions(+), 10 deletions(-)
diffs (truncated from 4807 to 300 lines):
diff -r eb0beb938dc6 -r 07ef7e415693 sys/arch/arm/arm/cpufunc.c
--- a/sys/arch/arm/arm/cpufunc.c Mon Jul 15 15:44:53 2002 +0000
+++ b/sys/arch/arm/arm/cpufunc.c Mon Jul 15 16:27:15 2002 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc.c,v 1.47 2002/07/10 07:00:50 ichiro Exp $ */
+/* $NetBSD: cpufunc.c,v 1.48 2002/07/15 16:27:15 ichiro Exp $ */
/*
* arm7tdmi support code Copyright (c) 2001 John Fremlin
@@ -555,6 +555,63 @@
};
#endif /* CPU_SA1100 || CPU_SA1110 */
+#ifdef CPU_IXP12X0
+struct cpu_functions ixp12x0_cpufuncs = {
+ /* CPU functions */
+
+ cpufunc_id, /* id */
+ cpufunc_nullop, /* cpwait */
+
+ /* MMU functions */
+
+ cpufunc_control, /* control */
+ cpufunc_domains, /* domain */
+ sa1_setttb, /* setttb */
+ cpufunc_faultstatus, /* faultstatus */
+ cpufunc_faultaddress, /* faultaddress */
+
+ /* TLB functions */
+
+ armv4_tlb_flushID, /* tlb_flushID */
+ sa1_tlb_flushID_SE, /* tlb_flushID_SE */
+ armv4_tlb_flushI, /* tlb_flushI */
+ (void *)armv4_tlb_flushI, /* tlb_flushI_SE */
+ armv4_tlb_flushD, /* tlb_flushD */
+ armv4_tlb_flushD_SE, /* tlb_flushD_SE */
+
+ /* Cache operations */
+
+ sa1_cache_syncI, /* icache_sync_all */
+ sa1_cache_syncI_rng, /* icache_sync_range */
+
+ sa1_cache_purgeD, /* dcache_wbinv_all */
+ sa1_cache_purgeD_rng, /* dcache_wbinv_range */
+/*XXX*/ sa1_cache_purgeD_rng, /* dcache_inv_range */
+ sa1_cache_cleanD_rng, /* dcache_wb_range */
+
+ sa1_cache_purgeID, /* idcache_wbinv_all */
+ sa1_cache_purgeID_rng, /* idcache_wbinv_range */
+
+ /* Other functions */
+
+ ixp12x0_drain_readbuf, /* flush_prefetchbuf */
+ armv4_drain_writebuf, /* drain_writebuf */
+ cpufunc_nullop, /* flush_brnchtgt_C */
+ (void *)cpufunc_nullop, /* flush_brnchtgt_E */
+
+ (void *)cpufunc_nullop, /* sleep */
+
+ /* Soft functions */
+
+ cpufunc_null_fixup, /* dataabt_fixup */
+ cpufunc_null_fixup, /* prefetchabt_fixup */
+
+ ixp12x0_context_switch, /* context_switch */
+
+ ixp12x0_setup /* cpu setup */
+};
+#endif /* CPU_IXP12X0 */
+
#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
defined(CPU_XSCALE_PXA2X0)
struct cpu_functions xscale_cpufuncs = {
@@ -693,7 +750,7 @@
#if defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3) || \
defined(CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_SA110) || \
- defined(CPU_SA1100) || defined(CPU_SA1110)
+ defined(CPU_SA1100) || defined(CPU_SA1110) || defined(CPU_IXP12X0)
/* Cache information for CPUs without cache type registers. */
struct cachetab {
u_int32_t ct_cpuid;
@@ -721,6 +778,7 @@
{ CPU_ID_SA110, CPU_CT_CTYPE_WB1, 0, 16384, 32, 32, 16384, 32, 32 },
{ CPU_ID_SA1100, CPU_CT_CTYPE_WB1, 0, 8192, 32, 32, 16384, 32, 32 },
{ CPU_ID_SA1110, CPU_CT_CTYPE_WB1, 0, 8192, 32, 32, 16384, 32, 32 },
+ { CPU_ID_IXP1200, CPU_CT_CTYPE_WB1, 0, 16384, 32, 32, 16384, 32, 32 }, /* XXX */
{ 0, 0, 0, 0, 0, 0, 0, 0}
};
@@ -751,7 +809,7 @@
arm_dcache_align_mask = arm_dcache_align - 1;
}
-#endif /* ARM2 || ARM250 || ARM3 || ARM6 || ARM7 || SA110 || SA1100 || SA1111 */
+#endif /* ARM2 || ARM250 || ARM3 || ARM6 || ARM7 || SA110 || SA1100 || SA1111 || IXP12X0 */
/*
* Cannot panic here as we may not have a console yet ...
@@ -851,6 +909,15 @@
return 0;
}
#endif /* CPU_SA1110 */
+#ifdef CPU_IXP12X0
+ if (cputype == CPU_ID_IXP1200) {
+ cpufuncs = ixp12x0_cpufuncs;
+ cpu_reset_needs_v4_MMU_disable = 1;
+ get_cachetype_table();
+ pmap_pte_init_generic();
+ return 0;
+ }
+#endif /* CPU_IXP12X0 */
#ifdef CPU_XSCALE_80200
if (cputype == CPU_ID_80200) {
int rev = cpufunc_id() & CPU_ID_REVISION_MASK;
@@ -1708,6 +1775,48 @@
}
#endif /* CPU_SA1100 || CPU_SA1110 */
+#if defined(CPU_IXP12X0)
+struct cpu_option ixp12x0_options[] = {
+ { "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
+ { "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
+ { "ixp12x0.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
+ { "ixp12x0.icache", BIC, OR, CPU_CONTROL_IC_ENABLE },
+ { "ixp12x0.dcache", BIC, OR, CPU_CONTROL_DC_ENABLE },
+ { "cpu.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },
+ { "cpu.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE },
+ { "ixp12x0.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },
+ { NULL, IGN, IGN, 0 }
+};
+
+void
+ixp12x0_setup(args)
+ char *args;
+{
+ int cpuctrl, cpuctrlmask;
+
+
+ cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE
+ | CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_SYST_ENABLE
+ | CPU_CONTROL_IC_ENABLE;
+
+ cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_AFLT_ENABLE
+ | CPU_CONTROL_DC_ENABLE | CPU_CONTROL_WBUF_ENABLE
+ | CPU_CONTROL_BEND_ENABLE | CPU_CONTROL_SYST_ENABLE
+ | CPU_CONTROL_ROM_ENABLE | CPU_CONTROL_IC_ENABLE
+ | CPU_CONTROL_VECRELOC;
+
+ cpuctrl = parse_cpu_options(args, ixp12x0_options, cpuctrl);
+
+ /* Clear out the cache */
+ cpu_idcache_wbinv_all();
+
+ /* Set the control register */
+ curcpu()->ci_ctrl = cpuctrl;
+ /* cpu_control(0xffffffff, cpuctrl); */
+ cpu_control(cpuctrlmask, cpuctrl);
+}
+#endif /* CPU_IXP12X0 */
+
#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
defined(CPU_XSCALE_PXA2X0)
struct cpu_option xscale_options[] = {
diff -r eb0beb938dc6 -r 07ef7e415693 sys/arch/arm/arm/cpufunc_asm_ixp12x0.S
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/arm/cpufunc_asm_ixp12x0.S Mon Jul 15 16:27:15 2002 +0000
@@ -0,0 +1,89 @@
+/* $NetBSD: cpufunc_asm_ixp12x0.S,v 1.1 2002/07/15 16:28:04 ichiro Exp $ */
+
+/*
+ * Copyright (c) 2002 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed for the NetBSD Project by
+ * Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <machine/cpu.h>
+#include <machine/asm.h>
+
+/*
+ * This function is the same as sa110_context_switch for now, the plan
+ * is to make use of the process id register to avoid cache flushes.
+ */
+ENTRY(ixp12x0_context_switch)
+ /*
+ * CF_CACHE_PURGE_ID will *ALWAYS* be called prior to this.
+ * Thus the data cache will contain only kernel data and the
+ * instruction cache will contain only kernel code, and all
+ * kernel mappings are shared by all processes.
+ */
+
+ /* Write the TTB */
+ mcr p15, 0, r0, c2, c0, 0
+
+ /* If we have updated the TTB we must flush the TLB */
+ mcr p15, 0, r0, c8, c7, 0 /* flush the I+D tlb */
+
+ /* Make sure that pipeline is emptied */
+ mov r0, r0
+ mov r0, r0
+ mov pc, lr
+
+ENTRY(ixp12x0_drain_readbuf)
+ mcr p15, 0, r0, c9, c0, 0 /* drain read buffer */
+ mov pc, lr
+
+/*
+ * Information for the IXP12X0 cache clean/purge functions:
+ *
+ * * Virtual address of the memory region to use
+ * * Size of memory region
+ */
+ .data
+
+ .global _C_LABEL(ixp12x0_cache_clean_addr)
+_C_LABEL(ixp12x0_cache_clean_addr):
+ .word 0xf0000000
+
+ .global _C_LABEL(ixp12x0_cache_clean_size)
+_C_LABEL(ixp12x0_cache_clean_size):
+ .word 0x00008000
+
+ .text
+
+Lixp12x0_cache_clean_addr:
+ .word _C_LABEL(ixp12x0_cache_clean_addr)
+Lixp12x0_cache_clean_size:
+ .word _C_LABEL(ixp12x0_cache_clean_size)
diff -r eb0beb938dc6 -r 07ef7e415693 sys/arch/arm/conf/files.arm
--- a/sys/arch/arm/conf/files.arm Mon Jul 15 15:44:53 2002 +0000
+++ b/sys/arch/arm/conf/files.arm Mon Jul 15 16:27:15 2002 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: files.arm,v 1.60 2002/05/03 16:46:52 rjs Exp $
+# $NetBSD: files.arm,v 1.61 2002/07/15 16:27:16 ichiro Exp $
# temporary define to allow easy moving to ../arch/arm/arm32
defflag ARM32
@@ -7,7 +7,7 @@
defflag opt_cputypes.h CPU_ARM2 CPU_ARM250 CPU_ARM3
defflag opt_cputypes.h CPU_ARM6 CPU_ARM7 CPU_ARM7TDMI CPU_ARM8
CPU_ARM9 CPU_SA110 CPU_SA1100 CPU_SA1110
- CPU_XSCALE_80200 CPU_XSCALE_80321
+ CPU_IXP12X0 CPU_XSCALE_80200 CPU_XSCALE_80321
CPU_XSCALE_PXA2X0
defparam opt_cpuoptions.h XSCALE_CCLKCFG
@@ -72,15 +72,18 @@
file arch/arm/arm/cpufunc_asm_arm9.S cpu_arm9
file arch/arm/arm/cpufunc_asm_armv4.S cpu_arm9 | cpu_sa110 |
cpu_sa1100 | cpu_sa1110 |
+ cpu_ixp12x0 |
cpu_xscale_80200 |
cpu_xscale_80321 |
cpu_xscale_pxa2x0
file arch/arm/arm/cpufunc_asm_sa1.S cpu_sa110 | cpu_sa1100 |
- cpu_sa1110
+ cpu_sa1110 |
+ cpu_ixp12x0
file arch/arm/arm/cpufunc_asm_sa11x0.S cpu_sa1100 | cpu_sa1110
file arch/arm/arm/cpufunc_asm_xscale.S cpu_xscale_80200 |
cpu_xscale_80321 |
cpu_xscale_pxa2x0
+file arch/arm/arm/cpufunc_asm_ixp12x0.S cpu_ixp12x0
file arch/arm/arm/process_machdep.c
file arch/arm/arm/procfs_machdep.c procfs
file arch/arm/arm/sig_machdep.c
diff -r eb0beb938dc6 -r 07ef7e415693 sys/arch/arm/include/cpuconf.h
--- a/sys/arch/arm/include/cpuconf.h Mon Jul 15 15:44:53 2002 +0000
+++ b/sys/arch/arm/include/cpuconf.h Mon Jul 15 16:27:15 2002 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuconf.h,v 1.2 2002/05/03 03:28:49 thorpej Exp $ */
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