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[src/trunk]: src/sys/dev/pci Don't use internal names to identify chips. Add...



details:   https://anonhg.NetBSD.org/src/rev/0778a7a4ab90
branches:  trunk
changeset: 533801:0778a7a4ab90
user:      thorpej <thorpej%NetBSD.org@localhost>
date:      Tue Jul 09 19:47:46 2002 +0000

description:
Don't use internal names to identify chips.  Add types for the
i82540, i82545, and i82546 (but don't match them yet).

diffstat:

 sys/dev/pci/if_wm.c |  178 +++++++++++++++++++++++++--------------------------
 1 files changed, 88 insertions(+), 90 deletions(-)

diffs (truncated from 434 to 300 lines):

diff -r 94353d4a1f8a -r 0778a7a4ab90 sys/dev/pci/if_wm.c
--- a/sys/dev/pci/if_wm.c       Tue Jul 09 19:43:57 2002 +0000
+++ b/sys/dev/pci/if_wm.c       Tue Jul 09 19:47:46 2002 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: if_wm.c,v 1.10 2002/07/09 14:52:37 thorpej Exp $       */
+/*     $NetBSD: if_wm.c,v 1.11 2002/07/09 19:47:46 thorpej Exp $       */
 
 /*
  * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
@@ -36,14 +36,13 @@
  */
 
 /*
- * Device driver for the Intel i82542 (``Wiseman''), i82543 (``Livengood''),
- * and i82544 (``Cordova'') Gigabit Ethernet chips.
+ * Device driver for the Intel i8254x family of Gigabit Ethernet chips.
  *
  * TODO (in order of importance):
  *
  *     - Fix hw VLAN assist.
  *
- *     - Make GMII work on the Livengood.
+ *     - Make GMII work on the i82543.
  *
  *     - Fix out-bound IP header checksums.
  *
@@ -292,10 +291,13 @@
 } while (/*CONSTCOND*/0)
 
 /* sc_type */
-#define        WM_T_WISEMAN_2_0        0       /* Wiseman (i82542) 2.0 (really old) */
-#define        WM_T_WISEMAN_2_1        1       /* Wiseman (i82542) 2.1+ (old) */
-#define        WM_T_LIVENGOOD          2       /* Livengood (i82543) */
-#define        WM_T_CORDOVA            3       /* Cordova (i82544) */
+#define        WM_T_82542_2_0          0       /* i82542 2.0 (really old) */
+#define        WM_T_82542_2_1          1       /* i82542 2.1+ (old) */
+#define        WM_T_82543              2       /* i82543 */
+#define        WM_T_82544              3       /* i82544 */
+#define        WM_T_82540              4       /* i82540 */
+#define        WM_T_82545              5       /* i82545 */
+#define        WM_T_82546              6       /* i82546 */
 
 /* sc_flags */
 #define        WM_F_HAS_MII            0x01    /* has MII */
@@ -409,11 +411,11 @@
 
 void   wm_gmii_reset(struct wm_softc *);
 
-int    wm_gmii_livengood_readreg(struct device *, int, int);
-void   wm_gmii_livengood_writereg(struct device *, int, int, int);
-
-int    wm_gmii_cordova_readreg(struct device *, int, int);
-void   wm_gmii_cordova_writereg(struct device *, int, int, int);
+int    wm_gmii_i82543_readreg(struct device *, int, int);
+void   wm_gmii_i82543_writereg(struct device *, int, int, int);
+
+int    wm_gmii_i82544_readreg(struct device *, int, int);
+void   wm_gmii_i82544_writereg(struct device *, int, int, int);
 
 void   wm_gmii_statchg(struct device *);
 
@@ -444,35 +446,31 @@
 } wm_products[] = {
        { PCI_VENDOR_INTEL,     PCI_PRODUCT_INTEL_82542,
          "Intel i82542 1000BASE-X Ethernet",
-         WM_T_WISEMAN_2_1,     WMP_F_1000X },
-
-       { PCI_VENDOR_INTEL,     PCI_PRODUCT_INTEL_82543_FIBER,
-         "Intel i82543 1000BASE-X Ethernet",
-         WM_T_LIVENGOOD,       WMP_F_1000X },
-
-       { PCI_VENDOR_INTEL,     PCI_PRODUCT_INTEL_82543_SC,
-         "Intel i82543-SC 1000BASE-X Ethernet",
-         WM_T_LIVENGOOD,       WMP_F_1000X },
-
-       { PCI_VENDOR_INTEL,     PCI_PRODUCT_INTEL_82543_COPPER,
-         "Intel i82543 1000BASE-T Ethernet",
-         WM_T_LIVENGOOD,       WMP_F_1000T },
-
-       { PCI_VENDOR_INTEL,     PCI_PRODUCT_INTEL_82544_XT,
-         "Intel i82544 1000BASE-T Ethernet",
-         WM_T_CORDOVA,         WMP_F_1000T },
-
-       { PCI_VENDOR_INTEL,     PCI_PRODUCT_INTEL_82544_XF,
-         "Intel i82544 1000BASE-X Ethernet",
-         WM_T_CORDOVA,         WMP_F_1000X },
-
-       { PCI_VENDOR_INTEL,     PCI_PRODUCT_INTEL_82544GC,
+         WM_T_82542_2_1,       WMP_F_1000X },
+
+       { PCI_VENDOR_INTEL,     PCI_PRODUCT_INTEL_82543GC_FIBER,
+         "Intel i82543GC 1000BASE-X Ethernet",
+         WM_T_82543,           WMP_F_1000X },
+
+       { PCI_VENDOR_INTEL,     PCI_PRODUCT_INTEL_82543GC_COPPER,
+         "Intel i82543GC 1000BASE-T Ethernet",
+         WM_T_82543,           WMP_F_1000T },
+
+       { PCI_VENDOR_INTEL,     PCI_PRODUCT_INTEL_82544EI_COPPER,
+         "Intel i82544EI 1000BASE-T Ethernet",
+         WM_T_82544,           WMP_F_1000T },
+
+       { PCI_VENDOR_INTEL,     PCI_PRODUCT_INTEL_82544EI_FIBER,
+         "Intel i82544EI 1000BASE-X Ethernet",
+         WM_T_82544,           WMP_F_1000X },
+
+       { PCI_VENDOR_INTEL,     PCI_PRODUCT_INTEL_82544GC_COPPER,
          "Intel i82544GC 1000BASE-T Ethernet",
-         WM_T_CORDOVA,         WMP_F_1000T },
-
-       { PCI_VENDOR_INTEL,     PCI_PRODUCT_INTEL_82544GC_64,
-         "Intel i82544GC 1000BASE-T Ethernet",
-         WM_T_CORDOVA,         WMP_F_1000T },
+         WM_T_82544,           WMP_F_1000T },
+
+       { PCI_VENDOR_INTEL,     PCI_PRODUCT_INTEL_82544GC_LOM,
+         "Intel i82544GC (LOM) 1000BASE-T Ethernet",
+         WM_T_82544,           WMP_F_1000T },
 
        { 0,                    0,
          NULL,
@@ -561,14 +559,14 @@
        printf(": %s, rev. %d\n", wmp->wmp_name, preg);
 
        sc->sc_type = wmp->wmp_type;
-       if (sc->sc_type < WM_T_LIVENGOOD) {
+       if (sc->sc_type < WM_T_82543) {
                if (preg < 2) {
-                       printf("%s: Wiseman must be at least rev. 2\n",
+                       printf("%s: i82542 must be at least rev. 2\n",
                            sc->sc_dev.dv_xname);
                        return;
                }
                if (preg < 3)
-                       sc->sc_type = WM_T_WISEMAN_2_0;
+                       sc->sc_type = WM_T_82542_2_0;
        }
 
        /*
@@ -594,10 +592,10 @@
                return;
        }
 
-       /* Enable bus mastering.  Disable MWI on the Wiseman 2.0. */
+       /* Enable bus mastering.  Disable MWI on the i82542 2.0. */
        preg = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
        preg |= PCI_COMMAND_MASTER_ENABLE;
-       if (sc->sc_type < WM_T_WISEMAN_2_1)
+       if (sc->sc_type < WM_T_82542_2_1)
                preg &= ~PCI_COMMAND_INVALIDATE_ENABLE;
        pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg);
 
@@ -727,12 +725,12 @@
         */
        wm_read_eeprom(sc, EEPROM_OFF_CFG1, 1, &cfg1);
        wm_read_eeprom(sc, EEPROM_OFF_CFG2, 1, &cfg2);
-       if (sc->sc_type >= WM_T_CORDOVA)
+       if (sc->sc_type >= WM_T_82544)
                wm_read_eeprom(sc, EEPROM_OFF_SWDPIN, 1, &swdpin);
 
        if (cfg1 & EEPROM_CFG1_ILOS)
                sc->sc_ctrl |= CTRL_ILOS;
-       if (sc->sc_type >= WM_T_CORDOVA) {
+       if (sc->sc_type >= WM_T_82544) {
                sc->sc_ctrl |=
                    ((swdpin >> EEPROM_SWDPIN_SWDPIO_SHIFT) & 0xf) <<
                    CTRL_SWDPIO_SHIFT;
@@ -746,7 +744,7 @@
        }
 
 #if 0
-       if (sc->sc_type >= WM_T_CORDOVA) {
+       if (sc->sc_type >= WM_T_82544) {
                if (cfg1 & EEPROM_CFG1_IPS0)
                        sc->sc_ctrl_ext |= CTRL_EXT_IPS;
                if (cfg1 & EEPROM_CFG1_IPS1)
@@ -771,9 +769,9 @@
 
        /*
         * Set up some register offsets that are different between
-        * the Wiseman and the Livengood and later chips.
+        * the i82542 and the i82543 and later chips.
         */
-       if (sc->sc_type < WM_T_LIVENGOOD) {
+       if (sc->sc_type < WM_T_82543) {
                sc->sc_rdt_reg = WMREG_OLD_RDT0;
                sc->sc_tdt_reg = WMREG_OLD_TDT;
        } else {
@@ -783,16 +781,16 @@
 
        /*
         * Determine if we should use flow control.  We should
-        * always use it, unless we're on a Wiseman < 2.1.
+        * always use it, unless we're on a i82542 < 2.1.
         */
-       if (sc->sc_type >= WM_T_WISEMAN_2_1)
+       if (sc->sc_type >= WM_T_82542_2_1)
                sc->sc_ctrl |= CTRL_TFCE | CTRL_RFCE;
 
        /*
         * Determine if we're TBI or GMII mode, and initialize the
         * media structures accordingly.
         */
-       if (sc->sc_type < WM_T_LIVENGOOD ||
+       if (sc->sc_type < WM_T_82543 ||
            (CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) {
                if (wmp->wmp_flags & WMP_F_1000T)
                        printf("%s: WARNING: TBIMODE set on 1000BASE-T "
@@ -818,17 +816,17 @@
        IFQ_SET_READY(&ifp->if_snd);
 
        /*
-        * If we're a Livengood or greater, we can support VLANs.
+        * If we're a i82543 or greater, we can support VLANs.
         */
-       if (sc->sc_type >= WM_T_LIVENGOOD)
+       if (sc->sc_type >= WM_T_82543)
                sc->sc_ethercom.ec_capabilities |=
                    ETHERCAP_VLAN_MTU /* XXXJRT | ETHERCAP_VLAN_HWTAGGING */;
 
        /*
         * We can perform TCPv4 and UDPv4 checkums in-bound.  Only
-        * on Livengood and later.
+        * on i82543 and later.
         */
-       if (sc->sc_type >= WM_T_LIVENGOOD)
+       if (sc->sc_type >= WM_T_82543)
                ifp->if_capabilities |=
                    IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4;
 
@@ -1447,7 +1445,7 @@
                /*
                 * XXX We should probably be using the statistics
                 * XXX registers, but I don't know if they exist
-                * XXX on chips before the Cordova.
+                * XXX on chips before the i82544.
                 */
 
 #ifdef WM_EVENT_COUNTERS
@@ -1837,7 +1835,7 @@
        sc->sc_txctx_ipcs = 0xffffffff;
        sc->sc_txctx_tucs = 0xffffffff;
 
-       if (sc->sc_type < WM_T_LIVENGOOD) {
+       if (sc->sc_type < WM_T_82543) {
                CSR_WRITE(sc, WMREG_OLD_TBDAH, 0);
                CSR_WRITE(sc, WMREG_OLD_TBDAL, WM_CDTXADDR(sc, 0));
                CSR_WRITE(sc, WMREG_OLD_TDLEN, sizeof(sc->sc_txdescs));
@@ -1871,7 +1869,7 @@
         * Initialize the receive descriptor and receive job
         * descriptor rings.
         */
-       if (sc->sc_type < WM_T_LIVENGOOD) {
+       if (sc->sc_type < WM_T_82543) {
                CSR_WRITE(sc, WMREG_OLD_RDBAH0, 0);
                CSR_WRITE(sc, WMREG_OLD_RDBAL0, WM_CDRXADDR(sc, 0));
                CSR_WRITE(sc, WMREG_OLD_RDLEN0, sizeof(sc->sc_rxdescs));
@@ -1931,7 +1929,7 @@
                CSR_WRITE(sc, WMREG_FCAH, FCAH_CONST);
                CSR_WRITE(sc, WMREG_FCT, ETHERTYPE_FLOWCONTROL);
 
-               if (sc->sc_type < WM_T_LIVENGOOD) {
+               if (sc->sc_type < WM_T_82543) {
                        CSR_WRITE(sc, WMREG_OLD_FCRTH, FCRTH_DFLT);
                        CSR_WRITE(sc, WMREG_OLD_FCRTL, FCRTL_DFLT);
                } else {
@@ -2004,7 +2002,7 @@
         * the register when we set the receive filter.  Use multicast
         * address offset type 0.
         *
-        * Only the Cordova has the ability to strip the incoming
+        * Only the i82544 has the ability to strip the incoming
         * CRC, so we don't enable that feature.
         */
        sc->sc_mchash_type = 0;
@@ -2213,7 +2211,7 @@
                ral_hi = 0;
        }
 
-       if (sc->sc_type >= WM_T_CORDOVA) {
+       if (sc->sc_type >= WM_T_82544) {
                CSR_WRITE(sc, WMREG_RAL_LO(WMREG_CORDOVA_RAL_BASE, idx),
                    ral_lo);
                CSR_WRITE(sc, WMREG_RAL_HI(WMREG_CORDOVA_RAL_BASE, idx),
@@ -2259,7 +2257,7 @@
        uint32_t hash, reg, bit;
        int i;
 
-       if (sc->sc_type >= WM_T_CORDOVA)
+       if (sc->sc_type >= WM_T_82544)
                mta_reg = WMREG_CORDOVA_MTA;
        else
                mta_reg = WMREG_MTA;
@@ -2308,7 +2306,7 @@
                hash |= 1U << bit;
 
                /* XXX Hardware bug?? */
-               if (sc->sc_type == WM_T_CORDOVA && (reg & 0xe) == 1) {
+               if (sc->sc_type == WM_T_82544 && (reg & 0xe) == 1) {
                        bit = CSR_READ(sc, mta_reg + ((reg - 1) << 2));



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