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[src/trunk]: src/sys/arch/hpcmips/vr add VR4181 clock control.
details: https://anonhg.NetBSD.org/src/rev/aed5932556bd
branches: trunk
changeset: 515545:aed5932556bd
user: sato <sato%NetBSD.org@localhost>
date: Fri Sep 28 10:25:15 2001 +0000
description:
add VR4181 clock control.
diffstat:
sys/arch/hpcmips/vr/cmureg.h | 91 ++++++++++++++++++++++++++++++++++++-----
sys/arch/hpcmips/vr/com_vrip.c | 9 ++-
sys/arch/hpcmips/vr/vrpiu.c | 11 ++--
3 files changed, 91 insertions(+), 20 deletions(-)
diffs (207 lines):
diff -r 6335888bbb6b -r aed5932556bd sys/arch/hpcmips/vr/cmureg.h
--- a/sys/arch/hpcmips/vr/cmureg.h Fri Sep 28 10:18:33 2001 +0000
+++ b/sys/arch/hpcmips/vr/cmureg.h Fri Sep 28 10:25:15 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cmureg.h,v 1.3 2001/05/17 05:04:30 sato Exp $ */
+/* $NetBSD: cmureg.h,v 1.4 2001/09/28 10:25:15 sato Exp $ */
/*-
* Copyright (c) 1999 SATO Kazumi. All rights reserved.
@@ -37,21 +37,90 @@
/*
* CMU (CLock MASK UNIT) Registers.
* start 0x0B000060 (Vr4102-4111)
- * start 0x0F000060 (Vr4122)
+ * start 0x0F000060 (Vr4122-4131)
+ * start 0x0A000004 (Vr4181)
*/
+#define CMUNOMASK 0
#define CMUCLKMASK 0x000 /* CMU Clock Mask Register */
+
+/* vr4102-4121 */
+#define VR4102_CMUMSKPCIU CMUNOMASK /* no PCICLK */
+#define VR4102_CMUMSKFFIR (1<<10) /* 1 supply 48MHz to FIR */
+#define VR4102_CMUMSKSHSP (1<<9) /* 1 supply 18.432MHz to HSP */
+#define VR4102_CMUMSKSSIU (1<<8) /* 1 supply 18.432MHz to SIU */
+#define VR4102_CMUMSKDSIU (1<<5) /* 1 supply Tclock to DSIU */
+#define VR4102_CMUMSKCSI CMUNOMASK /* no CSI clock */
+#define VR4102_CMUMSKFIR (1<<4) /* 1 supply Tclock to FIR */
+#define VR4102_CMUMSKKIU (1<<3) /* 1 supply Tclock to KIU */
+#define VR4102_CMUMSKAIU (1<<2) /* 1 supply Tclock to AIU */
+#define VR4102_CMUMSKSIU (1<<1) /* 1 supply Tclock to SIU */
+#define VR4102_CMUMSKPIU (1) /* 1 supply Tclock to PIU */
+
+/* vr4122-4131 */
#define VR4122_CMUMSKPCIU ((1<<13)|(1<<7)) /* 1 supply PCICLK */
#define VR4122_CMUMSKSCSI (1<<12) /* 1 supply CSI 18.432MHz clock */
#define VR4122_CMUMSKDSIU (1<<11) /* 1 supply DSIU 18.432MHz clock */
-#define CMUMSKFFIR (1<<10) /* 1 supply 48MHz to FIR */
-#define CMUMSKSHSP (1<<9) /* 1 supply 18.432MHz to HSP */ /* 4102-4121 */
-#define CMUMSKSSIU (1<<8) /* 1 supply 18.432MHz to SIU */
-#define CMUMSKDSIU (1<<5) /* 1 supply Tclock to DSIU */
-#define CMUMSKFIR (1<<4) /* 1 supply Tclock to FIR */
-#define CMUMSKKIU (1<<3) /* 1 supply Tclock to KIU */ /* 4102-4121 */
-#define CMUMSKAIU (1<<2) /* 1 supply Tclock to AIU */ /* 4102-4121 */
-#define CMUMSKSIU (1<<1) /* 1 supply Tclock to SIU */
-#define CMUMSKPIU (1) /* 1 supply Tclock to PIU */ /* 4102-4121 */
+#define VR4122_CMUMSKFFIR (1<<10) /* 1 supply 48MHz to FIR */
+#define VR4122_CMUMSKSHSP CMUNOMASK /* no HSP */
+#define VR4122_CMUMSKSSIU (1<<8) /* 1 supply 18.432MHz to SIU */
+#define VR4122_CMUMSKCSI (1<<6) /* 1 supply Tclock to CSI */
+#define VR4122_CMUMSKFIR (1<<4) /* 1 supply Tclock to FIR */
+#define VR4122_CMUMSKKIU CMUNOMASK /* no KIU */
+#define VR4122_CMUMSKAIU CMUNOMASK /* no AIU */
+#define VR4122_CMUMSKSIU (1<<1) /* 1 supply Tclock to SIU */
+#define VR4122_CMUMSKPIU CMUNOMASK /* no PIU */
+
+/* vr4181 */
+#define VR4181_CMUMSKPCIU CMUNOMASK /* no PCICLK */
+#define VR4181_CMUMSKHSP CMUNOMASK /* no HSP */
+#define VR4181_CMUMSKDSIU CMUNOMASK /* no DSIU */
+#define VR4181_CMUMSKCSI (1<<6) /* 1 supply PCLK to CSI */
+#define VR4181_CMUMSKFIR CMUNOMASK /* no FIR */
+#define VR4181_CMUMSKKIU CMUNOMASK /* no KIU */
+#define VR4181_CMUMSKAIU (1<<5) /* 1 supply PLCK to AIU */
+#define VR4181_CMUMSKPIU (1<<4) /* 1 supply PLCK to PIU */
+#define VR4181_CMUMSKADU (1<<3) /* 1 supply PLCK to ADU */
+#define VR4181_CMUMSKSSIU (1<<2) /* 1 supply 18.432MHz to SIU */
+#define VR4181_CMUMSKSADU (1<<1) /* 1 supply 18.432MHz to ADU */
+
+#if defined SINGLE_VRIP_BASE
+#ifdef VRGROUP_4102_4121
+#define CMUMASK_PIU VR4102_CMUMSKPIU
+#define CMUMASK_SIU (VR4102_CMUMSKSIU|VR4102_CMUMSKSSIU)
+#define CMUMASK_AIU VR4102_CMUMSKAIU
+#define CMUMASK_KIU VR4102_CMUMSKKIU
+#define CMUMASK_FIR (VR4102_CMUMSKFIR|VR4102_CMUMSKFFIR)
+#define CMUMASK_DSIU VR4102_CMUMSKDSIU
+#define CMUMASK_HSP VR4102_CMUMSKHSP
+#define CMUMASK_CSI VR4102_CMUMSKCSI
+#define CMUMASK_PCIU VR4102_CMUMSKPCIU
+#endif /* VRGROUP_4102_4121 */
+
+#ifdef VRGROUP_4122_4131
+#define CMUMASK_PIU VR4122_CMUMSKPIU
+#define CMUMASK_SIU (VR4122_CMUMSKSIU|VR4122_CMUMSKSSIU)
+#define CMUMASK_AIU VR4122_CMUMSKAIU
+#define CMUMASK_KIU VR4122_CMUMSKKIU
+#define CMUMASK_FIR (VR4122_CMUMSKFIR|VR4122_CMUMSKFFIR)
+#define CMUMASK_DSIU VR4122_CMUMSKDSIU
+#define CMUMASK_HSP VR4122_CMUMSKHSP
+#define CMUMASK_CSI (VR4122_CMUMSKSCSI|VR4122_CMUMSKCSI)
+#define CMUMASK_PCIU VR4122_CMUMSKPCIU
+#endif /* VRGROUP_4122_4131 */
+
+#ifdef VRGROUP_4181
+#define CMUMASK_PIU VR4181_CMUMSKPIU
+#define CMUMASK_SIU VR4181_CMUMSKSSIU
+#define CMUMASK_AIU VR4181_CMUMSKAIU
+#define CMUMASK_KIU VR4181_CMUMSKKIU
+#define CMUMASK_FIR VR4181_CMUMSKFIR
+#define CMUMASK_DSIU VR4181_CMUMSKDSIU
+#define CMUMASK_HSP VR4181_CMUMSKHSP
+#define CMUMASK_CSI VR4181_CMUMSKCSI
+#define CMUMASK_PCIU VR4181_CMUMSKPCIU
+#endif /* VRGROUP_4181 */
+
+#endif /* SINGLE_VRIP_BASE */
/* END cmureg.h */
diff -r 6335888bbb6b -r aed5932556bd sys/arch/hpcmips/vr/com_vrip.c
--- a/sys/arch/hpcmips/vr/com_vrip.c Fri Sep 28 10:18:33 2001 +0000
+++ b/sys/arch/hpcmips/vr/com_vrip.c Fri Sep 28 10:25:15 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: com_vrip.c,v 1.9 2001/09/16 05:32:20 uch Exp $ */
+/* $NetBSD: com_vrip.c,v 1.10 2001/09/28 10:25:16 sato Exp $ */
/*-
* Copyright (c) 1999 SASAKI Takesi. All rights reserved.
@@ -51,6 +51,7 @@
#include <machine/config_hook.h>
#include <hpcmips/vr/vr.h>
+#include <hpcmips/vr/vrcpudef.h>
#include <hpcmips/vr/vripvar.h>
#include <hpcmips/vr/cmureg.h>
#include <hpcmips/vr/siureg.h>
@@ -127,7 +128,7 @@
{
int port;
/* Platform dependent setting */
- __vrcmu_supply(CMUMSKSSIU | CMUMSKSIU, 1);
+ __vrcmu_supply(CMUMASK_SIU, 1);
if (find_comenableport_from_cfdata(&port))
__vrgiu_out(port, 1);
@@ -174,7 +175,7 @@
if (!va->va_cf || !va->va_cf->cf_clock)
return 0; /* not yet CMU attached. Try again later. */
- va->va_cf->cf_clock(va->va_cc, CMUMSKSSIU | CMUMSKSIU, 1);
+ va->va_cf->cf_clock(va->va_cc, CMUMASK_SIU, 1);
if (com_is_console(iot, va->va_addr, 0)) {
/*
@@ -221,7 +222,7 @@
sc->sc_frequency = VRCOM_FREQ;
/* Power management */
- va->va_cf->cf_clock(va->va_cc, CMUMSKSSIU | CMUMSKSIU, 1);
+ va->va_cf->cf_clock(va->va_cc, CMUMASK_SIU, 1);
/*
va->va_gf->gf_portwrite(va->va_gc, GIUPORT_COM, 1);
*/
diff -r 6335888bbb6b -r aed5932556bd sys/arch/hpcmips/vr/vrpiu.c
--- a/sys/arch/hpcmips/vr/vrpiu.c Fri Sep 28 10:18:33 2001 +0000
+++ b/sys/arch/hpcmips/vr/vrpiu.c Fri Sep 28 10:25:15 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: vrpiu.c,v 1.16 2001/09/24 14:29:30 takemura Exp $ */
+/* $NetBSD: vrpiu.c,v 1.17 2001/09/28 10:25:15 sato Exp $ */
/*
* Copyright (c) 1999-2001 Shin Takemura All rights reserved.
@@ -53,6 +53,7 @@
#include <dev/hpc/hpcbatterytable.h>
#include <hpcmips/hpcmips/machdep.h>
+#include <hpcmips/vr/vrcpudef.h>
#include <hpcmips/vr/vripvar.h>
#include <hpcmips/vr/cmureg.h>
#include <hpcmips/vr/vrpiuvar.h>
@@ -324,7 +325,7 @@
return EBUSY;
/* supply clock to PIU */
- __vrcmu_supply(CMUMSKPIU, 1);
+ __vrcmu_supply(CMUMASK_PIU, 1);
/* set scan interval */
vrpiu_write(sc, PIUSIVL_REG_W, sc->sc_interval);
@@ -377,7 +378,7 @@
vrpiu_write(sc, PIUCNT_REG_W, 0);
/* mask clock to PIU */
- __vrcmu_supply(CMUMSKPIU, 0);
+ __vrcmu_supply(CMUMASK_PIU, 0);
}
}
@@ -394,7 +395,7 @@
return EBUSY;
/* supply clock to PIU */
- __vrcmu_supply(CMUMSKPIU, 1);
+ __vrcmu_supply(CMUMASK_PIU, 1);
/* set scan interval */
vrpiu_write(sc, PIUSIVL_REG_W, sc->sc_interval);
@@ -449,7 +450,7 @@
vrpiu_write(sc, PIUCNT_REG_W, 0);
/* mask clock to PIU */
- __vrcmu_supply(CMUMSKPIU, 0);
+ __vrcmu_supply(CMUMASK_PIU, 0);
}
}
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