[src/trunk]: src/sys/arch/hpcmips/vr vr4122 releted definition.

[sato <sato%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/a030445df788
branches:  trunk
changeset: 510011:a030445df788
user:      sato <sato%NetBSD.org@localhost>
date:      Thu May 17 05:04:30 2001 +0000

description:
vr4122 releted definition.

diffstat:

 sys/arch/hpcmips/vr/cmureg.h |  16 ++++++++++------
 sys/arch/hpcmips/vr/rtcreg.h |  44 ++++++++++++++++++++++++++++++++++++--------
 2 files changed, 46 insertions(+), 14 deletions(-)

diffs (109 lines):

diff -r 61a53e7b38eb -r a030445df788 sys/arch/hpcmips/vr/cmureg.h
--- a/sys/arch/hpcmips/vr/cmureg.h      Thu May 17 02:31:26 2001 +0000
+++ b/sys/arch/hpcmips/vr/cmureg.h      Thu May 17 05:04:30 2001 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cmureg.h,v 1.2 2001/04/18 10:48:59 sato Exp $  */
+/*     $NetBSD: cmureg.h,v 1.3 2001/05/17 05:04:30 sato Exp $  */
 
 /*-
  * Copyright (c) 1999 SATO Kazumi. All rights reserved.
@@ -36,18 +36,22 @@
 
 /*
  *     CMU (CLock MASK UNIT) Registers.
- *             start 0x0B000060 
+ *             start 0x0B000060 (Vr4102-4111)
+ *             start 0x0F000060 (Vr4122)
  */
 
 #define        CMUCLKMASK              0x000   /* CMU Clock Mask Register */
+#define                VR4122_CMUMSKPCIU       ((1<<13)|(1<<7))        /* 1 supply PCICLK */
+#define                VR4122_CMUMSKSCSI       (1<<12)         /* 1 supply CSI 18.432MHz clock */
+#define                VR4122_CMUMSKDSIU       (1<<11)         /* 1 supply DSIU 18.432MHz clock */
 #define                CMUMSKFFIR              (1<<10)         /* 1 supply 48MHz to FIR */
-#define                CMUMSKSHSP              (1<<9)          /* 1 supply 18.432MHz to HSP */
+#define                CMUMSKSHSP              (1<<9)          /* 1 supply 18.432MHz to HSP */ /* 4102-4121 */
 #define                CMUMSKSSIU              (1<<8)          /* 1 supply 18.432MHz to SIU */
 #define                CMUMSKDSIU              (1<<5)          /* 1 supply Tclock to DSIU */
 #define                CMUMSKFIR               (1<<4)          /* 1 supply Tclock to FIR */
-#define                CMUMSKKIU               (1<<3)          /* 1 supply Tclock to KIU */
-#define                CMUMSKAIU               (1<<2)          /* 1 supply Tclock to AIU */
+#define                CMUMSKKIU               (1<<3)          /* 1 supply Tclock to KIU */ /* 4102-4121 */
+#define                CMUMSKAIU               (1<<2)          /* 1 supply Tclock to AIU */ /* 4102-4121 */
 #define                CMUMSKSIU               (1<<1)          /* 1 supply Tclock to SIU */
-#define                CMUMSKPIU               (1)             /* 1 supply Tclock to PIU */
+#define                CMUMSKPIU               (1)             /* 1 supply Tclock to PIU */ /* 4102-4121 */
 
 /* END cmureg.h */
diff -r 61a53e7b38eb -r a030445df788 sys/arch/hpcmips/vr/rtcreg.h
--- a/sys/arch/hpcmips/vr/rtcreg.h      Thu May 17 02:31:26 2001 +0000
+++ b/sys/arch/hpcmips/vr/rtcreg.h      Thu May 17 05:04:30 2001 +0000
@@ -1,8 +1,8 @@
-/*     $NetBSD: rtcreg.h,v 1.2 1999/12/07 04:54:54 sato Exp $  */
+/*     $NetBSD: rtcreg.h,v 1.3 2001/05/17 05:04:30 sato Exp $  */
 
 /*-
  * Copyright (c) 1999 Shin Takemura. All rights reserved.
- * Copyright (c) 1999 SATO Kazumi. All rights reserved.
+ * Copyright (c) 1999-2001 SATO Kazumi. All rights reserved.
  * Copyright (c) 1999 PocketBSD Project. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -61,7 +61,8 @@
 
 /*
  *     RTC (Real Time Clock Unit) Registers definitions.
- *             start 0x0B0000C0
+ *             start 0x0B0000C0 (Vr4102-4121)
+ *             start 0x0F000100 (Vr4122)
  */
 #define ETIME_L_REG_W          0x000   /* Elapsed Time L */
 #define ETIME_M_REG_W          0x002   /* Elapsed Time M */
@@ -95,15 +96,42 @@
 #define RTCL2_CNT_H_REG_W      0x01e   /* RTC Long 2 Count H */
 
 
-#define TCLK_L_REG_W           0x100   /* TCLK L */
-#define TCLK_H_REG_W           0x102   /* TCLK H */
+#define VR4102_TCLK_L_REG_W    0x100   /* TCLK L */
+#define VR4102_TCLK_H_REG_W    0x102   /* TCLK H */
+#define VR4122_TCLK_L_REG_W    0x020   /* TCLK L */
+#define VR4122_TCLK_H_REG_W    0x022   /* TCLK H */
+#if defined VRGROUP_4102_4121
+#define TCLK_L_REG_W           VR4102_TCLK_L_REG_W     /* TCLK L */
+#define TCLK_H_REG_W           VR4102_TCLK_H_REG_W     /* TCLK H */
+#endif /* VRGROUP_4102_4121 */
+#if defined VRGROUP_4122
+#define TCLK_L_REG_W           VR4122_TCLK_L_REG_W     /* TCLK L */
+#define TCLK_H_REG_W           VR4122_TCLK_H_REG_W     /* TCLK H */
+#endif /* VRGROUP_4122 */
 
 
-#define TCLK_CNT_L_REG_W       0x104   /* TCLK Count L */
-#define TCLK_CNT_H_REG_W       0x106   /* TCLK Count H */
+#define VR4102_TCLK_CNT_L_REG_W        0x104   /* TCLK Count L */
+#define VR4102_TCLK_CNT_H_REG_W        0x106   /* TCLK Count H */
+#define VR4122_TCLK_CNT_L_REG_W        0x024   /* TCLK Count L */
+#define VR4122_TCLK_CNT_H_REG_W        0x026   /* TCLK Count H */
+#if defined VRGROUP_4102_4121
+#define TCLK_CNT_L_REG_W       VR4102_TCLK_CNT_L_REG_W /* TCLK Count L */
+#define TCLK_CNT_H_REG_W       VR4102_TCLK_CNT_L_REG_W /* TCLK Count H */
+#endif /* VRGROUP_4102_4121 */
+#if defined VRGROUP_4122
+#define TCLK_CNT_L_REG_W       VR4122_TCLK_CNT_L_REG_W /* TCLK Count L */
+#define TCLK_CNT_H_REG_W       VR4122_TCLK_CNT_H_REG_W /* TCLK Count H */
+#endif /* VRGROUP_4122 */
 
 
-#define RTCINT_REG_W           0x11e   /* RTC intr reg. */
+#define VR4102_RTCINT_REG_W            0x11e   /* RTC intr reg. */
+#define VR4122_RTCINT_REG_W            0x03e   /* RTC intr reg. */
+#if defined VRGROUP_4102_4121
+#define RTCINT_REG_W           VR4102_RTCINT_REG_W     /* RTC intr reg. */
+#endif /* VRGROUP_4102_4121 */
+#if defined VRGROUP_4122
+#define RTCINT_REG_W           VR4122_RTCINT_REG_W     /* RTC intr reg. */
+#endif /* VRGROUP_4122 */
 
 #define                RTCINT_TCLOCK           (1<<3)  /* TClock */
 #define                RTCINT_RTCLONG2         (1<<2)  /* RTC Long 2 */