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[src/trunk]: src/sys/arch/arm32/podulebus Use bus_space functions for accessi...
details: https://anonhg.NetBSD.org/src/rev/d4a402f1e2cf
branches: trunk
changeset: 508892:d4a402f1e2cf
user: rearnsha <rearnsha%NetBSD.org@localhost>
date: Sat Apr 21 20:47:26 2001 +0000
description:
Use bus_space functions for accessing SBIC registers.
diffstat:
sys/arch/arm32/podulebus/asc.c | 11 ++++-
sys/arch/arm32/podulebus/ascreg.h | 4 +-
sys/arch/arm32/podulebus/sbic.c | 22 ++++----
sys/arch/arm32/podulebus/sbicreg.h | 84 +++++++++++++++++++++++++------------
sys/arch/arm32/podulebus/sbicvar.h | 5 +-
5 files changed, 82 insertions(+), 44 deletions(-)
diffs (281 lines):
diff -r fc9d2d32c9bf -r d4a402f1e2cf sys/arch/arm32/podulebus/asc.c
--- a/sys/arch/arm32/podulebus/asc.c Sat Apr 21 19:18:20 2001 +0000
+++ b/sys/arch/arm32/podulebus/asc.c Sat Apr 21 20:47:26 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: asc.c,v 1.30 2001/03/18 15:56:05 bjh21 Exp $ */
+/* $NetBSD: asc.c,v 1.31 2001/04/21 20:47:26 rearnsha Exp $ */
/*
* Copyright (c) 1996 Mark Brinicombe
@@ -159,7 +159,14 @@
* eveything is a valid dma address
*/
sbic->sc_dmamask = 0;
- sbic->sc_sbicp = (sbic_regmap_p) (sc->sc_podule->mod_base + ASC_SBIC);
+
+ /* Map sbic */
+ sbic->sc_sbicp.sc_sbiciot = pa->pa_iot;
+ if (bus_space_map (sbic->sc_sbicp.sc_sbiciot,
+ sc->sc_podule->mod_base + ASC_SBIC, ASC_SBIC_SPACE, 0,
+ &sbic->sc_sbicp.sc_sbicioh))
+ panic("%s: Cannot map SBIC\n", dp->dv_xname);
+
sbic->sc_clkfreq = sbic_clock_override ? sbic_clock_override : 143;
sbic->sc_adapter.scsipi_cmd = asc_scsicmd;
diff -r fc9d2d32c9bf -r d4a402f1e2cf sys/arch/arm32/podulebus/ascreg.h
--- a/sys/arch/arm32/podulebus/ascreg.h Sat Apr 21 19:18:20 2001 +0000
+++ b/sys/arch/arm32/podulebus/ascreg.h Sat Apr 21 20:47:26 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: ascreg.h,v 1.5 1997/01/06 04:48:02 mark Exp $ */
+/* $NetBSD: ascreg.h,v 1.6 2001/04/21 20:47:26 rearnsha Exp $ */
/*
* Copyright (c) 1996 Mark Brinicombe
@@ -119,6 +119,8 @@
#define ASC_SBIC 0x2000
#define ASC_SRAM 0x0000
+#define ASC_SBIC_SPACE 8
+
#define ASC_SRAM_BLKSIZE 0x1000
#define IS_IRQREQ 0x01
diff -r fc9d2d32c9bf -r d4a402f1e2cf sys/arch/arm32/podulebus/sbic.c
--- a/sys/arch/arm32/podulebus/sbic.c Sat Apr 21 19:18:20 2001 +0000
+++ b/sys/arch/arm32/podulebus/sbic.c Sat Apr 21 20:47:26 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: sbic.c,v 1.21 2001/04/19 17:30:20 rearnsha Exp $ */
+/* $NetBSD: sbic.c,v 1.22 2001/04/21 20:47:26 rearnsha Exp $ */
/*
* Copyright (c) 1994 Christian E. Hopps
@@ -865,7 +865,7 @@
SBIC_DEBUG(printf("sbicinit:\n"));
- regs = dev->sc_sbicp;
+ regs = &dev->sc_sbicp;
if ((dev->sc_flags & SBICF_ALIVE) == 0) {
TAILQ_INIT(&dev->ready_list);
@@ -927,7 +927,7 @@
SBIC_DEBUG(printf("sbicreset: %d\n", __LINE__));
- regs = dev->sc_sbicp;
+ regs = &dev->sc_sbicp;
SBIC_DEBUG(printf("sbicreset: regs = %08x\n", regs));
@@ -1410,7 +1410,7 @@
#endif
SBIC_TRACE(dev);
- regs = dev->sc_sbicp;
+ regs = &dev->sc_sbicp;
acb = dev->sc_nexus;
/* Make sure pointers are OK */
@@ -1690,7 +1690,7 @@
dev->target = xs->sc_link->scsipi_scsi.target;
dev->lun = xs->sc_link->scsipi_scsi.lun;
acb = dev->sc_nexus;
- regs = dev->sc_sbicp;
+ regs = &dev->sc_sbicp;
usedma = sbicdmaok(dev, xs);
@@ -1900,7 +1900,7 @@
/* int newtarget, newlun;*/
/* unsigned tcnt;*/
- regs = dev->sc_sbicp;
+ regs = &dev->sc_sbicp;
/*
* pending interrupt?
@@ -1950,7 +1950,7 @@
/* unsigned tcnt;*/
SBIC_TRACE(dev);
- regs = dev->sc_sbicp;
+ regs = &dev->sc_sbicp;
do {
GET_SBIC_asr (regs, asr);
@@ -2010,7 +2010,7 @@
int recvlen;
u_char asr, csr, *tmpaddr;
- regs = dev->sc_sbicp;
+ regs = &dev->sc_sbicp;
dev->sc_msg[0] = 0xff;
dev->sc_msg[1] = 0xff;
@@ -2285,7 +2285,7 @@
/* unsigned tcnt;*/
SBIC_TRACE(dev);
- regs = dev->sc_sbicp;
+ regs = &dev->sc_sbicp;
acb = dev->sc_nexus;
QPRINTF(("next[%02x,%02x]",asr,csr));
@@ -2723,7 +2723,7 @@
if (dev->sc_dmatimo > 1) {
printf("%s: dma timeout #%d\n",
dev->sc_dev.dv_xname, dev->sc_dmatimo - 1);
- GET_SBIC_asr(dev->sc_sbicp, asr);
+ GET_SBIC_asr(&dev->sc_sbicp, asr);
if (asr & SBIC_ASR_INT) {
/* We need to service a missed IRQ */
printf("Servicing a missed int:(%02x,%02x)->(%02x,??)\n",
@@ -2773,7 +2773,7 @@
int i;
s = splbio();
- regs = dev->sc_sbicp;
+ regs = &dev->sc_sbicp;
#if CSR_TRACE_SIZE
printf("csr trace: ");
i = csr_traceptr;
diff -r fc9d2d32c9bf -r d4a402f1e2cf sys/arch/arm32/podulebus/sbicreg.h
--- a/sys/arch/arm32/podulebus/sbicreg.h Sat Apr 21 19:18:20 2001 +0000
+++ b/sys/arch/arm32/podulebus/sbicreg.h Sat Apr 21 20:47:26 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: sbicreg.h,v 1.2 1997/01/03 23:26:22 mark Exp $ */
+/* $NetBSD: sbicreg.h,v 1.3 2001/04/21 20:47:27 rearnsha Exp $ */
/*
* Copyright (c) 1990 The Regents of the University of California.
@@ -306,28 +306,38 @@
/* approximate, but we won't do SBT on selects */
#define sbic_isa_select(cmd) (((cmd) > 0x5) && ((cmd) < 0xa))
-#define PAD(n) char n
#define SBIC_MACHINE_DMA_MODE SBIC_CTL_DMA
typedef struct {
- volatile unsigned char sbic_asr; /* r : Aux Status Register */
-#define sbic_address sbic_asr /* w : desired register no */
- PAD(pad1);
- PAD(pad2);
- PAD(pad3);
- volatile unsigned char sbic_value; /* rw: register value */
-} sbic_padded_ind_regmap_t;
-typedef volatile sbic_padded_ind_regmap_t *sbic_regmap_p;
+ bus_space_tag_t sc_sbiciot;
+ bus_space_handle_t sc_sbicioh;
+} sbic_regmap, *sbic_regmap_p;
+
+#define SBIC_ASR 0
+#define SBIC_ADDR 0
+#define SBIC_VAL 1
-#define sbic_read_reg(regs,regno,val) do { \
- (regs)->sbic_address = (regno); \
- (val) = (regs)->sbic_value; \
- } while (0)
+#define sbic_read_reg(regs,regno,val) do { \
+ bus_space_write_1((regs)->sc_sbiciot, (regs)->sc_sbicioh, SBIC_ADDR, \
+ (regno)); \
+ bus_space_barrier((regs)->sc_sbiciot, (regs)->sc_sbicioh, SBIC_ADDR, \
+ 2, BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ); \
+ (val) = bus_space_read_1((regs)->sc_sbiciot, (regs)->sc_sbicioh, \
+ SBIC_VAL); \
+ bus_space_barrier((regs)->sc_sbiciot, (regs)->sc_sbicioh, SBIC_ADDR, \
+ 2, BUS_SPACE_BARRIER_READ); \
+} while (0)
-#define sbic_write_reg(regs,regno,val) do { \
- (regs)->sbic_address = (regno); \
- (regs)->sbic_value = (val); \
- } while (0)
+#define sbic_write_reg(regs,regno,val) do { \
+ bus_space_write_1((regs)->sc_sbiciot, (regs)->sc_sbicioh, SBIC_ADDR, \
+ (regno)); \
+ bus_space_barrier((regs)->sc_sbiciot, (regs)->sc_sbicioh, SBIC_ADDR, \
+ 2, BUS_SPACE_BARRIER_WRITE); \
+ bus_space_write_1((regs)->sc_sbiciot, (regs)->sc_sbicioh, SBIC_VAL, \
+ (val)); \
+ bus_space_barrier((regs)->sc_sbiciot, (regs)->sc_sbicioh, SBIC_ADDR, \
+ 2, BUS_SPACE_BARRIER_WRITE); \
+} while (0)
#define SET_SBIC_myid(regs,val) sbic_write_reg(regs,SBIC_myid,val)
#define GET_SBIC_myid(regs,val) sbic_read_reg(regs,SBIC_myid,val)
@@ -386,26 +396,44 @@
#define SBIC_TC_PUT(regs,val) do { \
sbic_write_reg(regs,SBIC_count_hi,((val)>>16)); \
- (regs)->sbic_value = (val)>>8; \
- (regs)->sbic_value = (val); \
+ bus_space_write_1(regs->sc_sbiciot, regs->sc_sbicioh, SBIC_VAL, \
+ (val) >> 8); \
+ bus_space_barrier((regs)->sc_sbiciot, (regs)->sc_sbicioh, SBIC_VAL, \
+ 1, BUS_SPACE_BARRIER_WRITE); \
+ bus_space_write_1(regs->sc_sbiciot, regs->sc_sbicioh, SBIC_VAL, \
+ (val)); \
+ bus_space_barrier((regs)->sc_sbiciot, (regs)->sc_sbicioh, SBIC_ADDR, \
+ 2, BUS_SPACE_BARRIER_WRITE); \
} while (0)
+
#define SBIC_TC_GET(regs,val) do { \
sbic_read_reg(regs,SBIC_count_hi,(val)); \
- (val) = ((val)<<8) | (regs)->sbic_value; \
- (val) = ((val)<<8) | (regs)->sbic_value; \
+ (val) = ((val)<<8) | bus_space_read_1(regs->sc_sbiciot, \
+ regs->sc_sbicioh, SBIC_VAL); \
+ bus_space_barrier((regs)->sc_sbiciot, (regs)->sc_sbicioh, SBIC_VAL, \
+ 1, BUS_SPACE_BARRIER_READ); \
+ (val) = ((val)<<8) | bus_space_read_1(regs->sc_sbiciot, \
+ regs->sc_sbicioh, SBIC_VAL); \
} while (0)
#define SBIC_LOAD_COMMAND(regs,cmd,cmdsize) do { \
- int n=(cmdsize)-1; \
- char *ptr = (char*)(cmd); \
- sbic_write_reg(regs,SBIC_cdb1,*ptr++); \
- while (n-- > 0) (regs)->sbic_value = *ptr++; \
+ bus_space_write_1(regs->sc_sbiciot, regs->sc_sbicioh, SBIC_ADDR, \
+ SBIC_cdb1); \
+ bus_space_barrier((regs)->sc_sbiciot, (regs)->sc_sbicioh, SBIC_ADDR, \
+ 2, BUS_SPACE_BARRIER_WRITE); \
+ bus_space_write_multi_1(regs->sc_sbiciot, regs->sbic_ioh, SBIC_VAL, \
+ (char *)(cmd), cmdsize); \
+ bus_space_barrier((regs)->sc_sbiciot, (regs)->sc_sbicioh, SBIC_ADDR, \
+ 2, BUS_SPACE_BARRIER_WRITE); \
} while (0)
-#define GET_SBIC_asr(regs,val) (val) = (regs)->sbic_asr
+#define GET_SBIC_asr(regs,val) \
+ (val) = bus_space_read_1((regs)->sc_sbiciot, (regs)->sc_sbicioh, \
+ SBIC_ASR)
#define WAIT_CIP(regs) do { \
- while ((regs)->sbic_asr & SBIC_ASR_CIP) \
+ while (bus_space_read_1(regs->sc_sbiciot, regs->sc_sbicioh, SBIC_ASR) \
+ & SBIC_ASR_CIP) \
; \
} while (0)
diff -r fc9d2d32c9bf -r d4a402f1e2cf sys/arch/arm32/podulebus/sbicvar.h
--- a/sys/arch/arm32/podulebus/sbicvar.h Sat Apr 21 19:18:20 2001 +0000
+++ b/sys/arch/arm32/podulebus/sbicvar.h Sat Apr 21 20:47:26 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: sbicvar.h,v 1.5 2000/03/23 06:35:16 thorpej Exp $ */
+/* $NetBSD: sbicvar.h,v 1.6 2001/04/21 20:47:27 rearnsha Exp $ */
/*
* Copyright (c) 1990 The Regents of the University of California.
@@ -117,7 +117,8 @@
u_char lun;
struct scsipi_link sc_link; /* proto for sub devices */
struct scsipi_adapter sc_adapter;
- sbic_regmap_p sc_sbicp; /* the SBIC */
+ sbic_regmap sc_sbicp; /* Handle for the SBIC */
+
volatile void *sc_cregs; /* driver specific regs */
/* Lists of command blocks */
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