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[src/trunk]: src/sys/arch/hpcmips/vr - add VR4181 ICU register map.
details: https://anonhg.NetBSD.org/src/rev/da4c2976f0db
branches: trunk
changeset: 515498:da4c2976f0db
user: sato <sato%NetBSD.org@localhost>
date: Thu Sep 27 13:59:37 2001 +0000
description:
- add VR4181 ICU register map.
- add VR4181 intr levels.
- add VR4131 ICU register map.
- add VR4131 intr levels.
XXX: not yet tested these platform.
diffstat:
sys/arch/hpcmips/vr/icureg.h | 162 ++++++++++++++++++++++++++++++++++++------
1 files changed, 139 insertions(+), 23 deletions(-)
diffs (truncated from 374 to 300 lines):
diff -r f8d431b5c437 -r da4c2976f0db sys/arch/hpcmips/vr/icureg.h
--- a/sys/arch/hpcmips/vr/icureg.h Thu Sep 27 13:27:54 2001 +0000
+++ b/sys/arch/hpcmips/vr/icureg.h Thu Sep 27 13:59:37 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: icureg.h,v 1.4 2001/04/18 11:07:27 sato Exp $ */
+/* $NetBSD: icureg.h,v 1.5 2001/09/27 13:59:37 sato Exp $ */
/*-
* Copyright (c) 1999 Shin Takemura. All rights reserved.
@@ -49,6 +49,8 @@
#define NO_REG_W 0 /* no register */
+
+/* SYSINT1 & MSYSINT1 */
#define SYSINT1_REG_W 0x000 /* Level1 System intr reg 1 */
#define MSYSINT1_REG_W 0x00c /* Level1 Mask System intr reg 1 */
@@ -83,6 +85,7 @@
#define SYSINT1_BAT (1<<0) /* Battery intr */
+/* PIUINT & MPIUINT */
#define ICUPIUINT_REG_W 0x002 /* Level2 PIU intr reg */
#define MPIUINT_REG_W 0x00e /* Level2 Mask PIU intr reg */
@@ -93,19 +96,27 @@
#define PIUINT_PADLOST (1<<2) /* A/D data timeout intr */
#define PIUINT_PENCHG (1) /* Touch Panel contact intr */
+
+/* AIUINT & MAIUINT */
#define VR4102_AIUINT_REG_W 0x004 /* Level2 AIU intr reg */
#define VR4102_MAIUINT_REG_W 0x010 /* Level2 Mask AIU intr reg */
#define VR4122_AIUINT_REG_W NO_REG_W /* Level2 AIU intr reg */
#define VR4122_MAIUINT_REG_W NO_REG_W /* Level2 Mask AIU intr reg */
+#define VR4181_AIUINT_REG_W 0x004 /* Level2 AIU intr reg */
+#define VR4181_MAIUINT_REG_W 0x010 /* Level2 Mask AIU intr reg */
#if defined SINGLE_VRIP_BASE
#if defined VRGROUP_4102_4121
#define AIUINT_REG_W VR4102_AIUINT_REG_W
#define MAIUINT_REG_W VR4102_MAIUINT_REG_W
#endif /* VRGROUP_4102_4121 */
-#if defined VRGROUP_4122
+#if defined VRGROUP_4122_4131
#define AIUINT_REG_W VR4122_AIUINT_REG_W
#define MAIUINT_REG_W VR4122_MAIUINT_REG_W
-#endif /* VRGROUP_4122 */
+#endif /* VRGROUP_4122_4131 */
+#if defined VRGROUP_4181
+#define AIUINT_REG_W VR4181_AIUINT_REG_W
+#define MAIUINT_REG_W VR4181_MAIUINT_REG_W
+#endif /* VRGROUP_4181 */
#endif
#define AIUINT_INTMEND (1<<11) /* Audio input DMA buffer 2 page */
@@ -117,19 +128,26 @@
#define AIUINT_INTSIDLE (1<<1) /* Audio output idle intr */
+/* KIUINT & MKIUINT */
#define VR4102_KIUINT_REG_W 0x006 /* Level2 KIU intr reg */
#define VR4102_MKIUINT_REG_W 0x012 /* Level2 Mask KIU intr reg */
#define VR4122_KIUINT_REG_W NO_REG_W /* Level2 KIU intr reg */
#define VR4122_MKIUINT_REG_W NO_REG_W /* Level2 Mask KIU intr reg */
+#define VR4181_KIUINT_REG_W 0x118 /* Level2 KIU intr reg */
+#define VR4181_MKIUINT_REG_W 0x012 /* Level2 Mask KIU intr reg */
#if defined SINGLE_VRIP_BASE
#if defined VRGROUP_4102_4121
#define KIUINT_REG_W VR4102_KIUINT_REG_W
#define MKIUINT_REG_W VR4102_MKIUINT_REG_W
#endif /* VRGROUP_4102_4121 */
-#if defined VRGROUP_4122
+#if defined VRGROUP_4122_4131
#define KIUINT_REG_W VR4122_KIUINT_REG_W
#define MKIUINT_REG_W VR4122_MKIUINT_REG_W
-#endif /* VRGROUP_4122 */
+#endif /* VRGROUP_4122_4131 */
+#if defined VRGROUP_4181
+#define KIUINT_REG_W VR4181_KIUINT_REG_W
+#define MKIUINT_REG_W VR4181_MKIUINT_REG_W
+#endif /* VRGROUP_4181 */
#endif
#define KIUINT_KDATLOST (1<<2) /* Key scan data lost */
@@ -137,8 +155,27 @@
#define KIUINT_SCANINT (1) /* Key input detect intr */
-#define GIUINT_L_REG_W 0x008 /* Level2 GIU intr reg Low */
-#define MGIUINT_L_REG_W 0x014 /* Level2 Mask GIU intr reg Low */
+/* GIUINTL & MGIUINTL */
+#define VR4102_GIUINT_L_REG_W 0x008 /* Level2 GIU intr reg Low */
+#define VR4102_MGIUINT_L_REG_W 0x014 /* Level2 Mask GIU intr reg Low */
+#define VR4122_GIUINT_L_REG_W 0x008 /* Level2 GIU intr reg Low */
+#define VR4122_MGIUINT_L_REG_W 0x014 /* Level2 Mask GIU intr reg Low */
+#define VR4181_GIUINT_L_REG_W NO_REG_W /* Level2 GIU intr reg Low */
+#define VR4181_MGIUINT_L_REG_W NO_REG_W /* Level2 Mask GIU intr reg Low */
+#if defined SINGLE_VRIP_BASE
+#if defined VRGROUP_4102_4121
+#define GIUINT_L_REG_W VR4102_GIUINT_L_REG_W
+#define MGIUINT_L_REG_W VR4102_MGIUINT_L_REG_W
+#endif /* VRGROUP_4102_4121 */
+#if defined VRGROUP_4122_4131
+#define GIUINT_L_REG_W VR4122_GIUINT_L_REG_W
+#define MGIUINT_L_REG_W VR4122_MGIUINT_L_REG_W
+#endif /* VRGROUP_4122_4131 */
+#if defined VRGROUP_4181
+#define GIUINT_L_REG_W VR4181_GIUINT_L_REG_W
+#define MGIUINT_L_REG_W VR4181_MGIUINT_L_REG_W
+#endif /* VRGROUP_4181 */
+#endif
#define GIUINT_GPIO15 (1<<15) /* GPIO 15 */
#define GIUINT_GPIO14 (1<<14) /* GPIO 14 */
@@ -158,14 +195,35 @@
#define GIUINT_GPIO0 (1) /* GPIO 0 */
-#define DSIUINT_REG_W 0x00a /* Level2 DSIU intr reg */
-#define MDSIUINT_REG_W 0x016 /* Level2 Mask DSIU intr reg */
+/* DSIUINT & MDSIUINT */
+#define VR4102_DSIUINT_REG_W 0x00a /* Level2 DSIU intr reg */
+#define VR4102_MDSIUINT_REG_W 0x016 /* Level2 Mask DSIU intr reg */
+#define VR4122_DSIUINT_REG_W 0x00a /* Level2 DSIU intr reg */
+#define VR4122_MDSIUINT_REG_W 0x016 /* Level2 Mask DSIU intr reg */
+#define VR4181_DSIUINT_REG_W NO_REG_W /* Level2 DSIU intr reg */
+#define VR4181_MDSIUINT_REG_W NO_REG_W /* Level2 Mask DSIU intr reg */
+#if defined SINGLE_VRIP_BASE
+#if defined VRGROUP_4102_4121
+#define DSIUINT_REG_W VR4102_DSIUINT_REG_W
+#define MDSIUINT_REG_W VR4102_MDSIUINT_REG_W
+#endif /* VRGROUP_4102_4121 */
+#if defined VRGROUP_4122_4131
+#define DSIUINT_REG_W VR4122_DSIUINT_REG_W
+#define MDSIUINT_REG_W VR4122_MDSIUINT_REG_W
+#endif /* VRGROUP_4122_4131 */
+#if defined VRGROUP_4181
+#define DSIUINT_REG_W VR4181_DSIUINT_REG_W
+#define MDSIUINT_REG_W VR4181_MDSIUINT_REG_W
+#endif /* VRGROUP_4181 */
+#endif
#define DSIUINT_DCTS (1<<11) /* DCTS# change */
#define DSIUINT_SER0 (1<<10) /* Debug serial receive error */
#define DSIUINT_SR0 (1<<9) /* Debug serial receive */
#define DSIUINT_ST0 (1<<8) /* Debug serial transmit */
+
+/* NMI */
#define NMI_REG_W 0x018 /* NMI reg */
#define LOWBATT_NMIORINT (1) /* Low battery type */
@@ -173,6 +231,7 @@
#define LOWBATT_NMI (0) /* Low battery NMI */
+/* SOFTINT */
#define SOFTINT_REG_W 0x01a /* Software intr reg */
#define SOFTINT_MASK3 (1<<3) /* Softint3 mask */
@@ -192,19 +251,26 @@
#define SOFTINT_CLEAR0 (0) /* Softint0 clear */
+/* SYSINT2 & MSYSINT2 */
#define VR4102_SYSINT2_REG_W 0x180 /* Level1 System intr reg 2 */
#define VR4102_MSYSINT2_REG_W 0x186 /* Level1 Mask System intr reg 2 */
#define VR4122_SYSINT2_REG_W 0x020 /* Level1 System intr reg 2 */
#define VR4122_MSYSINT2_REG_W 0x026 /* Level1 Mask System intr reg 2 */
+#define VR4181_SYSINT2_REG_W 0x180 /* Level1 System intr reg 2 */
+#define VR4181_MSYSINT2_REG_W 0x186 /* Level1 Mask System intr reg 2 */
#if defined SINGLE_VRIP_BASE
#if defined VRGROUP_4102_4121
#define SYSINT2_REG_W VR4102_SYSINT2_REG_W
#define MSYSINT2_REG_W VR4102_MSYSINT2_REG_W
#endif /* VRGROUP_4102_4121 */
-#if defined VRGROUP_4122
+#if defined VRGROUP_4122_4131
#define SYSINT2_REG_W VR4122_SYSINT2_REG_W
#define MSYSINT2_REG_W VR4122_MSYSINT2_REG_W
-#endif /* VRGROUP_4122 */
+#endif /* VRGROUP_4122_4131 */
+#if defined VRGROUP_4181
+#define SYSINT2_REG_W VR4181_SYSINT2_REG_W
+#define MSYSINT2_REG_W VR4181_MSYSINT2_REG_W
+#endif /* VRGROUP_4181 */
#endif
#define SYSINT2_INT31 (1<<15)
@@ -221,27 +287,38 @@
#define SYSINT2_SCU (1<<7) /* SCU intr (=vr4122) */
#define SYSINT2_INT22 (1<<6)
#define SYSINT2_PCI (1<<6) /* PCI intr (=vr4122) */
+#define SYSINT2_LCD (1<<6) /* LCD intr (=vr4181) */
#define SYSINT2_DSIU (1<<5) /* DSUI intr */
+#define SYSINT2_DCU81 (1<<5) /* DCU intr (=4181) */
#define SYSINT2_FIR (1<<4) /* FIR intr */
#define SYSINT2_TCLK (1<<3) /* TClock Counter intr */
+#define SYSINT2_CSI81 (1<<3) /* CSI intr (=4181) */
#define SYSINT2_HSP (1<<2) /* HSP intr (4122>=4102)*/
+#define SYSINT2_ECU (1<<2) /* EUC intr (=4181)*/
#define SYSINT2_LED (1<<1) /* LED intr */
#define SYSINT2_RTCL2 (1<<0) /* RTCLong2 intr */
+/* GIUINTH & MGIUINTH */
#define VR4102_GIUINT_H_REG_W 0x182 /* Level2 GIU intr reg High */
#define VR4102_MGIUINT_H_REG_W 0x188 /* Level2 Mask GIU intr reg High */
#define VR4122_GIUINT_H_REG_W 0x022 /* Level2 GIU intr reg High */
#define VR4122_MGIUINT_H_REG_W 0x028 /* Level2 Mask GIU intr reg High */
+#define VR4181_GIUINT_H_REG_W NO_REG_W /* Level2 GIU intr reg High */
+#define VR4181_MGIUINT_H_REG_W NO_REG_W /* Level2 Mask GIU intr reg High */
#if defined SINGLE_VRIP_BASE
#if defined VRGROUP_4102_4121
#define GIUINT_H_REG_W VR4102_GIUINT_H_REG_W
#define MGIUINT_H_REG_W VR4102_MGIUINT_H_REG_W
#endif /* VRGROUP_4102_4121 */
-#if defined VRGROUP_4122
+#if defined VRGROUP_4122_4131
#define GIUINT_H_REG_W VR4122_GIUINT_H_REG_W
#define MGIUINT_H_REG_W VR4122_MGIUINT_H_REG_W
-#endif /* VRGROUP_4122 */
+#endif /* VRGROUP_4122_4131 */
+#if defined VRGROUP_4181
+#define GIUINT_H_REG_W VR4181_GIUINT_H_REG_W
+#define MGIUINT_H_REG_W VR4181_MGIUINT_H_REG_W
+#endif /* VRGROUP_4181 */
#endif
#define GIUINT_GPIO31 (1<<15) /* GPIO 31 */
@@ -262,19 +339,26 @@
#define GIUINT_GPIO16 (1) /* GPIO 16 */
+/* FIRINT & MFIRINT */
#define VR4102_FIRINT_REG_W 0x184 /* Level2 FIR intr reg */
#define VR4102_MFIRINT_REG_W 0x18a /* Level2 Mask FIR intr reg */
#define VR4122_FIRINT_REG_W 0x024 /* Level2 FIR intr reg */
#define VR4122_MFIRINT_REG_W 0x02a /* Level2 Mask FIR intr reg */
+#define VR4181_FIRINT_REG_W NO_REG_W /* Level2 FIR intr reg */
+#define VR4181_MFIRINT_REG_W NO_REG_W /* Level2 Mask FIR intr reg */
#if defined SINGLE_VRIP_BASE
#if defined VRGROUP_4102_4121
#define FIRINT_REG_W VR4102_FIRINT_REG_W
#define MFIRINT_REG_W VR4102_MFIRINT_REG_W
#endif /* VRGROUP_4102_4121 */
-#if defined VRGROUP_4122
+#if defined VRGROUP_4122_4131
#define FIRINT_REG_W VR4122_FIRINT_REG_W
#define MFIRINT_REG_W VR4122_MFIRINT_REG_W
-#endif /* VRGROUP_4122 */
+#endif /* VRGROUP_4122_4131 */
+#if defined VRGROUP_4181
+#define FIRINT_REG_W VR4181_FIRINT_REG_W
+#define MFIRINT_REG_W VR4181_MFIRINT_REG_W
+#endif /* VRGROUP_4181 */
#endif
#define FIRINT_FIR (1<<4) /* FIR intr */
@@ -283,53 +367,77 @@
#define FIRINT_RECV1 (1<<1) /* FIR DMA buf recv buffer1 */
#define FIRINT_TRNS1 (1) /* FIR DMA buf transmit buffer1 */
+
+/* PCIINT & MPCIINT */
#define VR4102_PCIINT_REG_W NO_REG_W /* Level2 PCI intr reg */
#define VR4102_MPCIINT_REG_W NO_REG_W /* Level2 PCI intr mask */
#define VR4122_PCIINT_REG_W 0x2c /* Level2 PCI intr reg */
#define VR4122_MPCIINT_REG_W 0x32 /* Level2 PCI intr mask */
+#define VR4181_PCIINT_REG_W NO_REG_W /* Level2 PCI intr reg */
+#define VR4181_MPCIINT_REG_W NO_REG_W /* Level2 PCI intr mask */
#if defined SINGLE_VRIP_BASE
#if defined VRGROUP_4102_4121
#define PCIINT_REG_W VR4102_PCIINT_REG_W
#define MPCIINT_REG_W VR4102_MPCIINT_REG_W
#endif /* VRGROUP_4102_4121 */
-#if defined VRGROUP_4122
+#if defined VRGROUP_4122_4131
#define PCIINT_REG_W VR4122_PCIINT_REG_W
#define MPCIINT_REG_W VR4122_MPCIINT_REG_W
-#endif /* VRGROUP_4122 */
+#endif /* VRGROUP_4122_4131 */
+#if defined VRGROUP_4181
+#define PCIINT_REG_W VR4181_PCIINT_REG_W
+#define MPCIINT_REG_W VR4181_MPCIINT_REG_W
+#endif /* VRGROUP_4181 */
#endif
#define PCIINT_INT0 (1) /* PCI INT 0 */
+
+/* SCUINT & MSCUINT */
#define VR4102_SCUINT_REG_W NO_REG_W /* Level2 SCU intr reg */
#define VR4102_MSCUINT_REG_W NO_REG_W /* Level2 SCU intr mask */
#define VR4122_SCUINT_REG_W 0x2e /* Level2 SCU intr reg */
#define VR4122_MSCUINT_REG_W 0x34 /* Level2 SCU intr mask */
+#define VR4181_SCUINT_REG_W NO_REG_W /* Level2 SCU intr reg */
+#define VR4181_MSCUINT_REG_W NO_REG_W /* Level2 SCU intr mask */
#if defined SINGLE_VRIP_BASE
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