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[src/trunk]: src/sys/arch/hpcmips improve interrupt response.
details: https://anonhg.NetBSD.org/src/rev/9878c2aa7b8b
branches: trunk
changeset: 515389:9878c2aa7b8b
user: uch <uch%NetBSD.org@localhost>
date: Sun Sep 23 14:32:52 2001 +0000
description:
improve interrupt response.
diffstat:
sys/arch/hpcmips/hpcmips/interrupt.c | 139 ++-----------------------------
sys/arch/hpcmips/include/intr.h | 3 +-
sys/arch/hpcmips/include/sysconf.h | 6 +-
sys/arch/hpcmips/tx/tx39.c | 17 +++-
sys/arch/hpcmips/tx/tx39icu.c | 78 +++++++++++++++--
sys/arch/hpcmips/vr/vr.c | 149 +++++++++++++++++++++++++---------
6 files changed, 208 insertions(+), 184 deletions(-)
diffs (truncated from 673 to 300 lines):
diff -r 1307ad0c03d1 -r 9878c2aa7b8b sys/arch/hpcmips/hpcmips/interrupt.c
--- a/sys/arch/hpcmips/hpcmips/interrupt.c Sun Sep 23 13:55:13 2001 +0000
+++ b/sys/arch/hpcmips/hpcmips/interrupt.c Sun Sep 23 14:32:52 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: interrupt.c,v 1.3 2001/09/15 19:51:38 uch Exp $ */
+/* $NetBSD: interrupt.c,v 1.4 2001/09/23 14:32:52 uch Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -44,97 +44,10 @@
#include <uvm/uvm_extern.h>
-#include <machine/locore.h> /* mips3_cp0_*() */
#include <machine/sysconf.h>
-#ifdef DEBUG
-#define STATIC
-#else
-#define STATIC static
-#endif
-
-#if defined(VR41XX) && defined(TX39XX)
-STATIC void (*__cpu_intr)(u_int32_t, u_int32_t, u_int32_t, u_int32_t);
-#define VR_INTR vr_intr
-#define TX_INTR tx_intr
-#elif defined(VR41XX)
-#define VR_INTR cpu_intr
-#elif defined(TX39XX)
-#define TX_INTR cpu_intr
-#endif
-
-/*
- * This is a mask of bits to clear in the SR when we go to a
- * given interrupt priority level.
- */
-#ifdef VR41XX
-const u_int32_t __ipl_sr_bits_vr[_IPL_N] = {
- 0, /* IPL_NONE */
-
- MIPS_SOFT_INT_MASK_0, /* IPL_SOFT */
-
- MIPS_SOFT_INT_MASK_0, /* IPL_SOFTCLOCK */
-
- MIPS_SOFT_INT_MASK_0|
- MIPS_SOFT_INT_MASK_1, /* IPL_SOFTNET */
-
- MIPS_SOFT_INT_MASK_0|
- MIPS_SOFT_INT_MASK_1, /* IPL_SOFTSERIAL */
-
- MIPS_SOFT_INT_MASK_0|
- MIPS_SOFT_INT_MASK_1|
- MIPS_INT_MASK_0, /* IPL_BIO */
-
- MIPS_SOFT_INT_MASK_0|
- MIPS_SOFT_INT_MASK_1|
- MIPS_INT_MASK_0, /* IPL_NET */
-
- MIPS_SOFT_INT_MASK_0|
- MIPS_SOFT_INT_MASK_1|
- MIPS_INT_MASK_0, /* IPL_{TTY,SERIAL} */
-
- MIPS_SOFT_INT_MASK_0|
- MIPS_SOFT_INT_MASK_1|
- MIPS_INT_MASK_0|
- MIPS_INT_MASK_1, /* IPL_{CLOCK,HIGH} */
-};
-#endif /* VR41XX */
-
-#ifdef TX39XX
-const u_int32_t __ipl_sr_bits_tx[_IPL_N] = {
- 0, /* IPL_NONE */
-
- MIPS_SOFT_INT_MASK_0, /* IPL_SOFT */
-
- MIPS_SOFT_INT_MASK_0, /* IPL_SOFTCLOCK */
-
- MIPS_SOFT_INT_MASK_0|
- MIPS_SOFT_INT_MASK_1, /* IPL_SOFTNET */
-
- MIPS_SOFT_INT_MASK_0|
- MIPS_SOFT_INT_MASK_1, /* IPL_SOFTSERIAL */
-
- MIPS_SOFT_INT_MASK_0|
- MIPS_SOFT_INT_MASK_1|
- MIPS_INT_MASK_2|
- MIPS_INT_MASK_4, /* IPL_BIO */
-
- MIPS_SOFT_INT_MASK_0|
- MIPS_SOFT_INT_MASK_1|
- MIPS_INT_MASK_2|
- MIPS_INT_MASK_4, /* IPL_NET */
-
- MIPS_SOFT_INT_MASK_0|
- MIPS_SOFT_INT_MASK_1|
- MIPS_INT_MASK_2|
- MIPS_INT_MASK_4, /* IPL_{TTY,SERIAL} */
-
- MIPS_SOFT_INT_MASK_0|
- MIPS_SOFT_INT_MASK_1|
- MIPS_INT_MASK_2|
- MIPS_INT_MASK_4, /* IPL_{CLOCK,HIGH} */
-};
-#endif /* TX39XX */
+extern const u_int32_t __ipl_sr_bits_vr[];
+extern const u_int32_t __ipl_sr_bits_tx[];
const u_int32_t ipl_si_to_sr[_IPL_NSOFT] = {
MIPS_SOFT_INT_MASK_0, /* IPL_SOFT */
@@ -146,7 +59,6 @@
const u_int32_t *ipl_sr_bits;
struct hpcmips_soft_intrhand *softnet_intrhand;
struct hpcmips_soft_intr hpcmips_soft_intrs[_IPL_NSOFT];
-STATIC void softintr(u_int32_t);
void
intr_init()
@@ -162,49 +74,22 @@
}
#if defined(VR41XX) && defined(TX39XX)
+/*
+ * cpu_intr:
+ *
+ * handle MIPS CPU interrupt.
+ * if VR41XX only or TX39XX only kernel, directly jump to each handler
+ * (tx/tx39icu.c, vr/vr.c), don't use this dispather.
+ *
+ */
void
cpu_intr(u_int32_t status, u_int32_t cause, u_int32_t pc, u_int32_t ipending)
{
- (*__cpu_intr)(status, caust, pc, ipending);
+ (*platform.cpu_intr)(status, cause, pc, ipending);
}
#endif /* VR41XX && TX39XX */
-#ifdef VR41XX
-void
-VR_INTR(u_int32_t status, u_int32_t cause, u_int32_t pc, u_int32_t ipending)
-{
- uvmexp.intrs++;
-
- if (ipending & MIPS_INT_MASK_5) {
- /*
- * Writing a value to the Compare register,
- * as a side effect, clears the timer
- * interrupt request.
- */
- mips3_cp0_compare_write(mips3_cp0_count_read());
- }
-
- if (ipending & MIPS3_HARD_INT_MASK)
- _splset((*platform.iointr)(status, cause, pc, ipending));
-
- softintr(ipending);
-}
-#endif /* VR41XX */
-
-#ifdef TX39XX
-void
-TX_INTR(u_int32_t status, u_int32_t cause, u_int32_t pc, u_int32_t ipending)
-{
- uvmexp.intrs++;
-
- if (ipending & MIPS_HARD_INT_MASK)
- _splset((*platform.iointr)(status, cause, pc, ipending));
-
- softintr(ipending);
-}
-#endif /* TX39XX */
-
/*
* softintr:
*
diff -r 1307ad0c03d1 -r 9878c2aa7b8b sys/arch/hpcmips/include/intr.h
--- a/sys/arch/hpcmips/include/intr.h Sun Sep 23 13:55:13 2001 +0000
+++ b/sys/arch/hpcmips/include/intr.h Sun Sep 23 14:32:52 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: intr.h,v 1.14 2001/09/16 15:45:44 uch Exp $ */
+/* $NetBSD: intr.h,v 1.15 2001/09/23 14:32:52 uch Exp $ */
/*
* Copyright (c) 1998 Jonathan Stone. All rights reserved.
@@ -148,6 +148,7 @@
};
void softintr_init(void);
+void softintr(u_int32_t);
void *softintr_establish(int, void (*)(void *), void *);
void softintr_disestablish(void *);
void softintr_dispatch(void);
diff -r 1307ad0c03d1 -r 9878c2aa7b8b sys/arch/hpcmips/include/sysconf.h
--- a/sys/arch/hpcmips/include/sysconf.h Sun Sep 23 13:55:13 2001 +0000
+++ b/sys/arch/hpcmips/include/sysconf.h Sun Sep 23 14:32:52 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: sysconf.h,v 1.10 2001/09/18 17:37:28 uch Exp $ */
+/* $NetBSD: sysconf.h,v 1.11 2001/09/23 14:32:52 uch Exp $ */
/*
* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
@@ -54,17 +54,17 @@
extern struct platform {
/*
+ * cpu_intr - interrupt handler
* cpu_idle - CPU dependend idle routine.
* cons_init - console initialization
- * iointr - I/O interrupt handler
* fb_init - frame buffer initialization
* mem_init - Count available memory
* reboot - reboot or powerdown
* clock -
*/
+ void (*cpu_intr)(u_int32_t, u_int32_t, u_int32_t, u_int32_t);
void (*cpu_idle)(void);
void (*cons_init)(void);
- int (*iointr)(u_int32_t, u_int32_t, u_int32_t, u_int32_t);
void (*fb_init)(caddr_t*);
void (*mem_init)(paddr_t);
void (*reboot)(int, char *);
diff -r 1307ad0c03d1 -r 9878c2aa7b8b sys/arch/hpcmips/tx/tx39.c
--- a/sys/arch/hpcmips/tx/tx39.c Sun Sep 23 13:55:13 2001 +0000
+++ b/sys/arch/hpcmips/tx/tx39.c Sun Sep 23 14:32:52 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tx39.c,v 1.26 2001/09/17 17:03:45 uch Exp $ */
+/* $NetBSD: tx39.c,v 1.27 2001/09/23 14:32:53 uch Exp $ */
/*-
* Copyright (c) 1999, 2000 The NetBSD Foundation, Inc.
@@ -36,6 +36,8 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
+#include "opt_vr41xx.h"
+#include "opt_tx39xx.h"
#include "opt_tx39_debug.h"
#include "m38813c.h"
#include "tc5165buf.h"
@@ -83,7 +85,14 @@
#endif
void tx_init(void);
-int tx39icu_intr(u_int32_t, u_int32_t, u_int32_t, u_int32_t);
+#if defined(VR41XX) && defined(TX39XX)
+#define TX_INTR tx_intr
+#else
+#define TX_INTR cpu_intr /* locore_mips3 directly call this */
+#endif
+
+extern void TX_INTR(u_int32_t, u_int32_t, u_int32_t, u_int32_t);
+
void tx39clock_cpuspeed(int *, int *);
/* TX39-specific initialization vector */
@@ -92,7 +101,6 @@
void tx_mem_init(paddr_t);
void tx_find_dram(paddr_t, paddr_t);
void tx_reboot(int, char *);
-int tx_intr(u_int32_t, u_int32_t, u_int32_t, u_int32_t);
void
tx_init()
@@ -105,12 +113,13 @@
/*
* Platform Specific Function Hooks
*/
+ platform.cpu_intr = TX_INTR;
platform.cpu_idle = NULL; /* not implemented yet */
platform.cons_init = tx_cons_init;
platform.fb_init = tx_fb_init;
platform.mem_init = tx_mem_init;
platform.reboot = tx_reboot;
- platform.iointr = tx39icu_intr;
+
model = MIPS_PRID_REV(cpu_id);
diff -r 1307ad0c03d1 -r 9878c2aa7b8b sys/arch/hpcmips/tx/tx39icu.c
--- a/sys/arch/hpcmips/tx/tx39icu.c Sun Sep 23 13:55:13 2001 +0000
+++ b/sys/arch/hpcmips/tx/tx39icu.c Sun Sep 23 14:32:52 2001 +0000
@@ -1,7 +1,7 @@
-/* $NetBSD: tx39icu.c,v 1.13 2001/09/18 17:37:28 uch Exp $ */
+/* $NetBSD: tx39icu.c,v 1.14 2001/09/23 14:32:53 uch Exp $ */
/*-
- * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc.
+ * Copyright (c) 1999-2001 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
@@ -36,6 +36,9 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
+#include "opt_vr41xx.h"
+#include "opt_tx39xx.h"
+
#include "opt_tx39_debug.h"
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