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[src/trunk]: src/sys/arch/next68k Apply patches from Christian Limpach:
details: https://anonhg.NetBSD.org/src/rev/977ac2042c2e
branches: trunk
changeset: 533957:977ac2042c2e
user: christos <christos%NetBSD.org@localhost>
date: Thu Jul 11 16:03:09 2002 +0000
description:
Apply patches from Christian Limpach:
- NeXT label reading support
- SCSI dma fixes
- media support for if_xe.c
Some of these need more cleanup, but at least make SCSI support usable on
the NeXT.
diffstat:
sys/arch/next68k/dev/bmapreg.h | 42 +
sys/arch/next68k/dev/esp.c | 711 ++++++++++++++++++++++------
sys/arch/next68k/dev/espvar.h | 6 +-
sys/arch/next68k/dev/if_xe.c | 22 +-
sys/arch/next68k/dev/mb8795.c | 396 ++++++++++-----
sys/arch/next68k/dev/mb8795var.h | 10 +-
sys/arch/next68k/dev/nextdma.c | 79 ++-
sys/arch/next68k/dev/nextdmavar.h | 5 +-
sys/arch/next68k/include/disklabel.h | 46 +-
sys/arch/next68k/next68k/autoconf.c | 96 +++-
sys/arch/next68k/next68k/disksubr.c | 369 +++++++++++++-
sys/arch/next68k/next68k/nextrom.c | 17 +-
sys/arch/next68k/stand/boot/Makefile | 10 +-
sys/arch/next68k/stand/boot/boot.c | 51 +-
sys/arch/next68k/stand/boot/conf.c | 4 +-
sys/arch/next68k/stand/boot/dmareg.h | 4 +-
sys/arch/next68k/stand/boot/en.c | 15 +-
sys/arch/next68k/stand/boot/installboot.sh | 3 +-
sys/arch/next68k/stand/boot/machdep.c | 29 +-
sys/arch/next68k/stand/boot/scsi.c | 137 +++--
sys/arch/next68k/stand/boot/sd.c | 108 ++-
21 files changed, 1682 insertions(+), 478 deletions(-)
diffs (truncated from 3432 to 300 lines):
diff -r 20a3e0fc7d81 -r 977ac2042c2e sys/arch/next68k/dev/bmapreg.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/next68k/dev/bmapreg.h Thu Jul 11 16:03:09 2002 +0000
@@ -0,0 +1,42 @@
+/* $NetBSD: bmapreg.h,v 1.1 2002/07/11 16:03:09 christos Exp $ */
+
+/*
+ * Copyright (c) 2002 Christian Limpach
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Christian Limpach
+ * 4. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#define BMAP_DDIR (12 * 4)
+#define BMAP_DDIR_UTPENABLE_MASK 0x80|0x10
+
+#define BMAP_DATA (13 * 4)
+#define BMAP_DATA_UTPCARRIER_MASK 0x20
+#define BMAP_DATA_UTPENABLE 0x80|0x10
+
+/* Size of register area to be mapped */
+#define BMAP_SIZE 14 * 4
diff -r 20a3e0fc7d81 -r 977ac2042c2e sys/arch/next68k/dev/esp.c
--- a/sys/arch/next68k/dev/esp.c Thu Jul 11 15:45:10 2002 +0000
+++ b/sys/arch/next68k/dev/esp.c Thu Jul 11 16:03:09 2002 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: esp.c,v 1.36 2002/05/20 18:03:03 jdolecek Exp $ */
+/* $NetBSD: esp.c,v 1.37 2002/07/11 16:03:10 christos Exp $ */
/*-
* Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
@@ -120,9 +120,14 @@
#ifdef ESP_DEBUG
int esp_debug = 0;
#define DPRINTF(x) if (esp_debug) printf x;
+int esplogshow = 0;
+char esplog[8192+100];
+char *esplogp = esplog;
+#define ESPLOGIF 10 && (esplogp < (esplog + 8192))
#else
#define DPRINTF(x)
#endif
+#define PRINTF(x) printf x;
void espattach_intio __P((struct device *, struct device *, void *));
@@ -320,10 +325,10 @@
/* @@@ Some ESP_DCTL bits probably need setting */
NCR_WRITE_REG(sc, ESP_DCTL,
- ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_RESET);
+ ESPDCTL_16MHZ | ESPDCTL_INTENB | ESPDCTL_RESET);
DELAY(10);
DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL)));
- NCR_WRITE_REG(sc, ESP_DCTL, ESPDCTL_20MHZ | ESPDCTL_INTENB);
+ NCR_WRITE_REG(sc, ESP_DCTL, ESPDCTL_16MHZ | ESPDCTL_INTENB);
DELAY(10);
DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL)));
@@ -426,25 +431,68 @@
bus_space_write_1(esc->sc_bst, esc->sc_bsh, reg, val);
}
+volatile u_int32_t save1;
+
+#define xADDR 0x0211a000
+int doze __P((volatile int));
+int
+doze(c)
+ volatile int c;
+{
+/* static int tmp1; */
+ u_int32_t tmp1;
+ volatile u_int8_t tmp2;
+ volatile u_int8_t *reg = (volatile u_int8_t *)IIOV(xADDR);
+ if (c > 244) return (0);
+ if (c == 0) return (0);
+/* ((*(volatile u_long *)IIOV(NEXT_P_INTRMASK))&=(~NEXT_I_BIT(x))) */
+ (*reg) = 0;
+ (*reg) = 0;
+ do {
+ save1 = (*reg);
+ tmp2 = *(reg + 3);
+ tmp1 = tmp2;
+ } while (tmp1 <= c);
+ return (0);
+}
+
int
esp_dma_isintr(sc)
struct ncr53c9x_softc *sc;
{
struct esp_softc *esc = (struct esp_softc *)sc;
+ if (INTR_OCCURRED(NEXT_I_SCSI)) {
+ if (ESPLOGIF) *esplogp++ = 'i';
+ NCR_WRITE_REG(sc, ESP_DCTL, ESPDCTL_16MHZ | ESPDCTL_INTENB | (esc->sc_datain ? ESPDCTL_DMARD : 0));
+ return (1);
+ } else {
+ return (0);
+ }
+}
+
+int
+esp_dma_intr(sc)
+ struct ncr53c9x_softc *sc;
+{
+ struct esp_softc *esc = (struct esp_softc *)sc;
int r = (INTR_OCCURRED(NEXT_I_SCSI));
+ int flushcount;
+ r = 1;
+ if (ESPLOGIF) *esplogp++ = 'I';
if (r) {
-
+ /* printf ("esp_dma_isintr start\n"); */
{
- int flushcount;
- int s;
- s = spldma();
+ int s = spldma();
+ void *ndmap = esc->sc_scsi_dma._nd_map;
+ int ndidx = esc->sc_scsi_dma._nd_idx;
+ splx(s);
flushcount = 0;
#ifdef ESP_DEBUG
- esp_dma_nest++;
+/* esp_dma_nest++; */
if (esp_debug) {
char sbuf[256];
@@ -455,106 +503,171 @@
}
#endif
- while (esp_dma_isactive(sc)) {
- flushcount++;
+ while (!nextdma_finished(&esc->sc_scsi_dma)) { /* esp_dma_isactive(sc)) { */
+ if (ESPLOGIF) *esplogp++ = 'w';
+ if (ESPLOGIF) {
+ sprintf (esplogp, "f%dm%dl%dw", NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF,
+ NCR_READ_REG((sc), NCR_TCM), NCR_READ_REG((sc), NCR_TCL));
+ esplogp += strlen (esplogp);
+ }
+ if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)
+ flushcount=5;
+ NCR_WRITE_REG(sc, ESP_DCTL, ESPDCTL_16MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD |
+ (esc->sc_datain ? ESPDCTL_DMARD : 0));
+
+ s = spldma();
+ while (ndmap == esc->sc_scsi_dma._nd_map && ndidx == esc->sc_scsi_dma._nd_idx &&
+ !(bus_space_read_4(esc->sc_scsi_dma.nd_bst, esc->sc_scsi_dma.nd_bsh, DD_CSR)
+ & 0x08000000) &&
+ ++flushcount < 5) {
+ splx(s);
+ if (flushcount < 10) if (ESPLOGIF) *esplogp++ = 'F';
+ NCR_WRITE_REG(sc, ESP_DCTL, ESPDCTL_FLUSH |
+ ESPDCTL_16MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD |
+ (esc->sc_datain ? ESPDCTL_DMARD : 0));
+ doze(0x32);
+ NCR_WRITE_REG(sc, ESP_DCTL,
+ ESPDCTL_16MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD |
+ (esc->sc_datain ? ESPDCTL_DMARD : 0));
+ doze(0x32);
+ s = spldma();
+ }
+ if (ESPLOGIF) *esplogp++ = '0' + flushcount;
+ if (flushcount > 4) {
+ int next;
+ int onext = 0;
+ splx(s);
+ DPRINTF (("DMA reset\n"));
+ while (((next = bus_space_read_4(esc->sc_scsi_dma.nd_bst, esc->sc_scsi_dma.nd_bsh, DD_NEXT)) !=
+ (bus_space_read_4(esc->sc_scsi_dma.nd_bst, esc->sc_scsi_dma.nd_bsh, DD_LIMIT) & 0x7FFFFFFF)) &&
+ onext != next) {
+ onext = next;
+ DELAY(50);
+ }
+ if (ESPLOGIF) *esplogp++ = 'R';
+ NCR_WRITE_REG(sc, ESP_DCTL, ESPDCTL_16MHZ | ESPDCTL_INTENB);
+ if (ESPLOGIF) {
+ sprintf (esplogp, "ff:%d tcm:%d tcl:%d ",
+ NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF,
+ NCR_READ_REG((sc), NCR_TCM), NCR_READ_REG((sc), NCR_TCL));
+ esplogp += strlen (esplogp);
+ }
+ s = spldma();
+ nextdma_reset (&esc->sc_scsi_dma);
+ splx(s);
+ goto out;
+ }
+ splx(s);
#ifdef DIAGNOSTIC
- r = (INTR_OCCURRED(NEXT_I_SCSI));
- if (!r) panic("esp intr enabled but dma failed to flush");
-#endif
-#ifdef DIAGNOSTIC
-#if 0
- if ((esc->sc_loaded & (ESP_LOADED_TAIL/* |ESP_UNLOADED_MAIN */))
- != (ESP_LOADED_TAIL /* |ESP_UNLOADED_MAIN */)) {
- if (esc->sc_datain) {
- NCR_WRITE_REG(sc, ESP_DCTL,
- ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD);
- } else {
- NCR_WRITE_REG(sc, ESP_DCTL,
- ESPDCTL_20MHZ | ESPDCTL_INTENB);
- }
- next_dma_print(&esc->sc_scsi_dma);
- esp_dma_print(sc);
- printf("%s: unexpected flush: tc=0x%06x\n",
- sc->sc_dev.dv_xname,
- (((sc->sc_cfg2 & NCRCFG2_FE)
- ? NCR_READ_REG(sc, NCR_TCH) : 0)<<16)|
- (NCR_READ_REG(sc, NCR_TCM)<<8)|
- NCR_READ_REG(sc, NCR_TCL));
- ncr53c9x_readregs(sc);
- printf("%s: readregs[intr=%02x,stat=%02x,step=%02x]\n",
- sc->sc_dev.dv_xname,
- sc->sc_espintr, sc->sc_espstat, sc->sc_espstep);
- panic("%s: flushing flushing non-tail dma\n",
- sc->sc_dev.dv_xname);
+ if (flushcount > 4) {
+ if (ESPLOGIF) *esplogp++ = '+';
+ printf("%s: unexpected flushcount %d on %s\n",sc->sc_dev.dv_xname,
+ flushcount, esc->sc_datain ? "read" : "write");
}
#endif
+
+ if (!nextdma_finished(&esc->sc_scsi_dma)) { /* esp_dma_isactive(sc)) { */
+ if (ESPLOGIF) *esplogp++ = '1';
+ }
+ flushcount = 0;
+ s = spldma();
+ ndmap = esc->sc_scsi_dma._nd_map;
+ ndidx = esc->sc_scsi_dma._nd_idx;
+ splx(s);
+
+ goto loop;
+
+ loop:
+ }
+ goto out;
+ out:
+
+#ifdef ESP_DEBUG
+/* esp_dma_nest--; */
#endif
- DPRINTF(("%s: flushing dma, count = %d\n", sc->sc_dev.dv_xname,flushcount));
- if (esc->sc_datain) {
- NCR_WRITE_REG(sc, ESP_DCTL,
- ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_DMARD | ESPDCTL_FLUSH);
- DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL)));
- NCR_WRITE_REG(sc, ESP_DCTL,
- ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_DMARD);
- } else {
- NCR_WRITE_REG(sc, ESP_DCTL,
- ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_FLUSH);
- DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL)));
- NCR_WRITE_REG(sc, ESP_DCTL,
- ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD);
- }
- DPRINTF(("esp dctl is 0x%02x\n",NCR_READ_REG(sc,ESP_DCTL)));
+
+ }
+
+ doze (0x32);
+ NCR_WRITE_REG(sc, ESP_DCTL, ESPDCTL_16MHZ | ESPDCTL_INTENB | (esc->sc_datain ? ESPDCTL_DMARD : 0));
+ if (ESPLOGIF) *esplogp++ = 'b';
+
+ while (esc->sc_datain != -1) DELAY(50);
+
+ if (esc->sc_dmaaddr) {
+ bus_size_t xfer_len = 0;
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