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[src/trunk]: src/sys/arch/arm Default all XScale core processors to the read/...
details: https://anonhg.NetBSD.org/src/rev/f4336b2ba352
branches: trunk
changeset: 525545:f4336b2ba352
user: thorpej <thorpej%NetBSD.org@localhost>
date: Fri Apr 12 21:52:45 2002 +0000
description:
Default all XScale core processors to the read/write-allocate write-back
cache mode. Add a new XSCALE_CACHE_WRITE_THROUGH option for people who
are paranoid about the cache-related errata (you *do* have to line up
the planets correctly to trip them, but having the option is useful).
diffstat:
sys/arch/arm/arm/cpufunc.c | 4 ++--
sys/arch/arm/arm32/pmap.c | 37 +++++++++++++++++++------------------
sys/arch/arm/include/arm32/pmap.h | 5 +----
3 files changed, 22 insertions(+), 24 deletions(-)
diffs (102 lines):
diff -r 33a0ce58852c -r f4336b2ba352 sys/arch/arm/arm/cpufunc.c
--- a/sys/arch/arm/arm/cpufunc.c Fri Apr 12 21:45:13 2002 +0000
+++ b/sys/arch/arm/arm/cpufunc.c Fri Apr 12 21:52:45 2002 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc.c,v 1.41 2002/04/12 18:50:31 thorpej Exp $ */
+/* $NetBSD: cpufunc.c,v 1.42 2002/04/12 21:52:45 thorpej Exp $ */
/*
* arm7tdmi support code Copyright (c) 2001 John Fremlin
@@ -830,7 +830,7 @@
cpu_reset_needs_v4_MMU_disable = 1; /* XScale needs it */
get_cachetype_cp15();
- pmap_pte_init_i80200();
+ pmap_pte_init_xscale();
return 0;
}
#endif /* CPU_XSCALE_80200 */
diff -r 33a0ce58852c -r f4336b2ba352 sys/arch/arm/arm32/pmap.c
--- a/sys/arch/arm/arm32/pmap.c Fri Apr 12 21:45:13 2002 +0000
+++ b/sys/arch/arm/arm32/pmap.c Fri Apr 12 21:52:45 2002 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.c,v 1.94 2002/04/10 17:39:31 thorpej Exp $ */
+/* $NetBSD: pmap.c,v 1.95 2002/04/12 21:52:47 thorpej Exp $ */
/*
* Copyright (c) 2002 Wasabi Systems, Inc.
@@ -143,7 +143,7 @@
#include <machine/param.h>
#include <arm/arm32/katelib.h>
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.94 2002/04/10 17:39:31 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.95 2002/04/12 21:52:47 thorpej Exp $");
#ifdef PMAP_DEBUG
#define PDEBUG(_lev_,_stat_) \
if (pmap_debug_level >= (_lev_)) \
@@ -3814,6 +3814,23 @@
pte_l2_s_cache_mode = L2_B|L2_C|L2_XSCALE_T_TEX(TEX_XSCALE_X);
pte_l2_s_cache_mask = L2_S_CACHE_MASK_xscale;
+#ifdef XSCALE_CACHE_WRITE_THROUGH
+ /*
+ * Some versions of the XScale core have various bugs in
+ * their cache units, the work-around for which is to run
+ * the cache in write-through mode. Unfortunately, this
+ * has a major (negative) impact on performance. So, we
+ * go ahead and run fast-and-loose, in the hopes that we
+ * don't line up the planets in a way that will trip the
+ * bugs.
+ *
+ * However, we give you the option to be slow-but-correct.
+ */
+ pte_l1_s_cache_mode = L1_S_C;
+ pte_l2_l_cache_mode = L2_C;
+ pte_l2_s_cache_mode = L2_C;
+#endif /* XSCALE_CACHE_WRITE_THROUGH */
+
pte_l2_s_prot_u = L2_S_PROT_U_xscale;
pte_l2_s_prot_w = L2_S_PROT_W_xscale;
pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale;
@@ -3826,22 +3843,6 @@
pmap_zero_page_func = pmap_zero_page_xscale;
}
-#if defined(CPU_XSCALE_80200)
-void
-pmap_pte_init_i80200(void)
-{
-
- /*
- * Use write-through caching on the i80200 to work around
- * bugs in its cache unit.
- */
- pmap_pte_init_xscale();
- pte_l1_s_cache_mode = L1_S_C;
- pte_l2_l_cache_mode = L2_C;
- pte_l2_s_cache_mode = L2_C;
-}
-#endif /* CPU_XSCALE_80200 */
-
/*
* xscale_setup_minidata:
*
diff -r 33a0ce58852c -r f4336b2ba352 sys/arch/arm/include/arm32/pmap.h
--- a/sys/arch/arm/include/arm32/pmap.h Fri Apr 12 21:45:13 2002 +0000
+++ b/sys/arch/arm/include/arm32/pmap.h Fri Apr 12 21:52:45 2002 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.h,v 1.52 2002/04/12 18:50:32 thorpej Exp $ */
+/* $NetBSD: pmap.h,v 1.53 2002/04/12 21:52:48 thorpej Exp $ */
/*
* Copyright (c 2002 Wasabi Systems, Inc.
@@ -272,9 +272,6 @@
void pmap_zero_page_xscale(paddr_t);
void pmap_pte_init_xscale(void);
-#if defined(CPU_XSCALE_80200)
-void pmap_pte_init_i80200(void);
-#endif /* CPU_XSCALE_80200 */
void xscale_setup_minidata(vaddr_t, vaddr_t, paddr_t);
#endif /* ARM_MMU_XSCALE == 1 */
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