Source-Changes-HG archive
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]
[src/trunk]: src/sys/arch/news68k Make it possible to enable/disable DC_BE an...
details: https://anonhg.NetBSD.org/src/rev/09de824eaadb
branches: trunk
changeset: 499041:09de824eaadb
user: tsutsui <tsutsui%NetBSD.org@localhost>
date: Thu Nov 09 14:17:19 2000 +0000
description:
Make it possible to enable/disable DC_BE and IC_BE bits in %cacr at runtime
and enable them on news1200/1400/1500 (which have no L2cache).
diffstat:
sys/arch/news68k/include/cpu.h | 7 +++-
sys/arch/news68k/news68k/genassym.cf | 16 +++++++--
sys/arch/news68k/news68k/locore.s | 57 +++++++++++++++++++++++++----------
3 files changed, 57 insertions(+), 23 deletions(-)
diffs (225 lines):
diff -r 639d65f563fb -r 09de824eaadb sys/arch/news68k/include/cpu.h
--- a/sys/arch/news68k/include/cpu.h Thu Nov 09 13:32:06 2000 +0000
+++ b/sys/arch/news68k/include/cpu.h Thu Nov 09 14:17:19 2000 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.h,v 1.6 2000/10/04 16:26:43 tsutsui Exp $ */
+/* $NetBSD: cpu.h,v 1.7 2000/11/09 14:17:19 tsutsui Exp $ */
/*
* Copyright (c) 1988 University of Utah.
@@ -72,6 +72,9 @@
#define IC_CLEAR (DC_WA|DC_ENABLE|IC_CLR|IC_ENABLE)
#define DC_CLEAR (DC_WA|DC_CLR|DC_ENABLE|IC_ENABLE)
+#define DCIC_CLR (DC_CLR|IC_CLR)
+#define CACHE_BE (DC_BE|IC_BE)
+
#endif
/*
@@ -183,7 +186,7 @@
#define NEWS1200 1
extern int cpuspeed;
-extern char *intiobase, *intiolimit;
+extern char *intiobase, *intiolimit, *extiobase;
extern u_int intiobase_phys, intiotop_phys;
extern u_int extiobase_phys, extiotop_phys;
extern u_int intrcnt[];
diff -r 639d65f563fb -r 09de824eaadb sys/arch/news68k/news68k/genassym.cf
--- a/sys/arch/news68k/news68k/genassym.cf Thu Nov 09 13:32:06 2000 +0000
+++ b/sys/arch/news68k/news68k/genassym.cf Thu Nov 09 14:17:19 2000 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: genassym.cf,v 1.5 2000/09/15 17:15:06 tsutsui Exp $
+# $NetBSD: genassym.cf,v 1.6 2000/11/09 14:17:20 tsutsui Exp $
#
# Copyright (c) 1982, 1990, 1993
@@ -162,11 +162,19 @@
define EXTIOTOP1200 EXTIOTOP1200
define FC_USERD FC_USERD
define FC_SUPERD FC_SUPERD
+
+define DC_FREEZE DC_FREEZE
+define DC_BE DC_BE
+define DC_CLR DC_CLR
+define IC_BE IC_BE
+define IC_CLR IC_CLR
+
+define CACHE40_ON CACHE40_ON
+
define CACHE_ON CACHE_ON
define CACHE_OFF CACHE_OFF
-define CACHE_CLR CACHE_CLR
-define IC_CLEAR IC_CLEAR
-define DC_CLEAR DC_CLEAR
+define DCIC_CLR DCIC_CLR
+define CACHE_BE CACHE_BE
# pte/ste bits
define PG_V PG_V
diff -r 639d65f563fb -r 09de824eaadb sys/arch/news68k/news68k/locore.s
--- a/sys/arch/news68k/news68k/locore.s Thu Nov 09 13:32:06 2000 +0000
+++ b/sys/arch/news68k/news68k/locore.s Thu Nov 09 14:17:19 2000 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.s,v 1.12 2000/10/14 16:23:33 tsutsui Exp $ */
+/* $NetBSD: locore.s,v 1.13 2000/11/09 14:17:20 tsutsui Exp $ */
/*
* Copyright (c) 1988 University of Utah.
@@ -149,12 +149,15 @@
movl #CACHE_OFF,%d0
movc %d0,%cacr | clear and disable on-chip cache(s)
- movl #0x200,%d0 | data freeze bit
+ movl #DC_FREEZE,%d0 | data freeze bit
movc %d0,%cacr | only exists on 68030
movc %cacr,%d0 | read it back
tstl %d0 | zero?
jeq Lnot68030 | yes, we have 68020/68040
+ movl #CACHE_OFF,%d0
+ movc %d0,%cacr | clear data freeze bit
+
RELOC(mmutype,%a0)
movl #MMU_68030,%a0@
RELOC(cputype,%a0)
@@ -200,10 +203,10 @@
jra Lcom030
Lnot1200:
- tstl %d0 | news1700?
+ tstl %d0 | news1400/1500/1600/1700?
jne Lnotyet | no, then skip
- /* news1700 */
+ /* news1400/1500/1600/1700 */
/* XXX Are these needed?*/
sf 0xe1280000 | AST disable (???)
sf 0xe1180000 | level2 interrupt disable (???)
@@ -213,12 +216,20 @@
moveb #0x36,0xe0c80000 | XXX reset FDC for PWS-1560
/* XXX */
- /* news1700 - 68030 CPU/MMU, 68882 FPU */
+ /* news1400/1500/1600/1700 - 68030 CPU/MMU, 68882 FPU */
RELOC(systype,%a0)
movl #NEWS1700,%a0@
- RELOC(ectype, %a0)
- movl #EC_PHYS,%a0@ | news1700 have a phisical address cache
+
+ cmpb #0xf2,0xe1c00000 | read model id from idrom
+ jle 1f | news1600/1700 ?
+ RELOC(ectype, %a0) | no, we are news1400/1500
+ movl #EC_NONE,%a0 | and do not have L2 cache
+ jra 2f
+1:
+ RELOC(ectype, %a0) | yes, we are news1600/1700
+ movl #EC_PHYS,%a0@ | and have a phisical address cache
+2:
/*
* Fix up the physical addresses of the news1700's onboard
* I/O registers.
@@ -361,7 +372,7 @@
.word 0xf518 | pflusha
movl #0x8000,%d0
.long 0x4e7b0003 | movc %d0,%tc
- movl #0x80008000,%d0
+ movl #CACHE40_ON,%d0
movc %d0,%cacr | turn on both caches
jmp Lenab1
Lmotommu2:
@@ -404,7 +415,11 @@
tstl _C_LABEL(mmutype)
jpl Lenab3 | 68851 implies no d-cache
movl #CACHE_ON,%d0
- movc %d0,%cacr | clear cache(s)
+ tstl _C_LABEL(ectype) | have external cache?
+ jne 1f | Yes, skip
+ orl #CACHE_BE,%d0 | set cache burst enable
+1:
+ movc %d0,%cacr | clear cache
tstl _C_LABEL(ectype) | have external cache?
jeq Lenab3 | No, skip
movl _C_LABEL(cache_clr),%a0
@@ -1171,7 +1186,8 @@
tstl _C_LABEL(mmutype) | MMU type?
pflusha | flush entire TLB
jpl Lmc68851a | 68851 implies no d-cache
- movl #DC_CLEAR,%d0
+ movc %cacr,%d0
+ orl #DC_CLR,%d0
movc %d0,%cacr | invalidate on-chip d-cache
#if 0
jmp _C_LABEL(_DCIA)
@@ -1187,7 +1203,8 @@
movl %sp@(4),%a0 | get addr to flush
jpl Lmc68851b | is 68851?
pflush #0,#0,%a0@ | flush address from both sides
- movl #DC_CLEAR,%d0
+ movc %cacr,%d0
+ orl #DC_CLR,%d0
movc %d0,%cacr | invalidate on-chip data cache
rts
Lmc68851b:
@@ -1201,7 +1218,8 @@
tstl _C_LABEL(mmutype) | MMU type?
jpl Lmc68851c | 68851?
pflush #4,#4 | flush supervisor TLB entries
- movl #DC_CLEAR,%d0
+ movc %cacr,%d0
+ orl #DC_CLR,%d0
movc %d0,%cacr | invalidate on-chip d-cache
rts
Lmc68851c:
@@ -1218,7 +1236,8 @@
tstl _C_LABEL(mmutype) | MMU type?
jpl Lmc68851d | 68851?
pflush #0,#4 | flush user TLB entries
- movl #DC_CLEAR,%d0
+ movc %cacr,%d0
+ orl #DC_CLR,%d0
movc %d0,%cacr | invalidate on-chip d-cache
rts
Lmc68851d:
@@ -1232,7 +1251,8 @@
* Invalidate instruction cache
*/
ENTRY(ICIA)
- movl #IC_CLEAR,%d0
+ movc %cacr,%d0
+ orl #IC_CLR,%d0
movc %d0,%cacr | invalidate i-cache
#if 0
tstl _C_LABEL(ectype) | got external PAC?
@@ -1263,7 +1283,8 @@
_C_LABEL(_DCIS):
_C_LABEL(_DCIU):
#if 0
- movl #DC_CLEAR,%d0
+ movc %cacr,%d0
+ orl #DC_CLR,%d0
movc %d0,%cacr
#endif
tstl _C_LABEL(ectype) | got external VAC?
@@ -1276,7 +1297,8 @@
ENTRY(PCIA)
#if 0
- movl #DC_CLEAR,%d0
+ movc %cacr,%d0
+ orl #DC_CLR,%d0
movc %d0,%cacr | invalidate on-chip d-cache
#endif
tstl _C_LABEL(ectype) | got external PAC?
@@ -1333,7 +1355,8 @@
lea _C_LABEL(protorp),%a0 | CRP prototype
movl %d0,%a0@(4) | stash USTP
pmove %a0@,%crp | load root pointer
- movl #CACHE_CLR,%d0
+ movc %cacr,%d0
+ orl #DCIC_CLR,%d0
movc %d0,%cacr | invalidate cache(s)
rts
Home |
Main Index |
Thread Index |
Old Index