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[src/trunk]: src/sys/arch/macppc/macppc Add minimal support of openpic.
details: https://anonhg.NetBSD.org/src/rev/b9ec7eebca8d
branches: trunk
changeset: 482108:b9ec7eebca8d
user: tsubai <tsubai%NetBSD.org@localhost>
date: Mon Feb 14 12:45:52 2000 +0000
description:
Add minimal support of openpic.
diffstat:
sys/arch/macppc/macppc/autoconf.c | 22 +--
sys/arch/macppc/macppc/extintr.c | 357 +++++++++++++++++++++++++++++++----
sys/arch/macppc/macppc/openpicreg.h | 89 ++++++++
3 files changed, 399 insertions(+), 69 deletions(-)
diffs (truncated from 623 to 300 lines):
diff -r 1c5bc0a90f0c -r b9ec7eebca8d sys/arch/macppc/macppc/autoconf.c
--- a/sys/arch/macppc/macppc/autoconf.c Mon Feb 14 12:37:35 2000 +0000
+++ b/sys/arch/macppc/macppc/autoconf.c Mon Feb 14 12:45:52 2000 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: autoconf.c,v 1.20 2000/02/08 20:02:13 tsubai Exp $ */
+/* $NetBSD: autoconf.c,v 1.21 2000/02/14 12:45:52 tsubai Exp $ */
/*
* Copyright (C) 1995, 1996 Wolfgang Solfrank.
@@ -58,11 +58,6 @@
struct device *booted_device; /* boot device */
int booted_partition; /* ...and partition on that device */
-#define INT_ENABLE_REG (interrupt_reg + 0x24)
-#define INT_CLEAR_REG (interrupt_reg + 0x28)
-u_char *interrupt_reg;
-
-#define HEATHROW_FCR_OFFSET 0x38
u_int *heathrow_FCR = NULL;
/*
@@ -71,22 +66,9 @@
void
cpu_configure()
{
- int node, reg[5];
int msr;
- node = OF_finddevice("mac-io");
- if (node == -1)
- node = OF_finddevice("/pci/mac-io");
- if (node != -1 &&
- OF_getprop(node, "assigned-addresses", reg, sizeof(reg)) != -1) {
- interrupt_reg = mapiodev(reg[2], NBPG);
- heathrow_FCR = mapiodev(reg[2] + HEATHROW_FCR_OFFSET, 4);
- } else
- interrupt_reg = mapiodev(0xf3000000, NBPG);
-
- out32rb(INT_ENABLE_REG, 0); /* disable all intr. */
- out32rb(INT_CLEAR_REG, 0xffffffff); /* clear pending intr. */
-
+ init_interrupt();
calc_delayconst();
canonicalize_bootpath();
diff -r 1c5bc0a90f0c -r b9ec7eebca8d sys/arch/macppc/macppc/extintr.c
--- a/sys/arch/macppc/macppc/extintr.c Mon Feb 14 12:37:35 2000 +0000
+++ b/sys/arch/macppc/macppc/extintr.c Mon Feb 14 12:45:52 2000 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: extintr.c,v 1.11 2000/02/11 13:15:43 tsubai Exp $ */
+/* $NetBSD: extintr.c,v 1.12 2000/02/14 12:45:52 tsubai Exp $ */
/*-
* Copyright (c) 1995 Per Fogelstrom
@@ -39,6 +39,7 @@
*
* @(#)isa.c 7.2 (Berkeley) 5/12/91
*/
+
#include <sys/param.h>
#include <sys/malloc.h>
#include <sys/kernel.h>
@@ -46,45 +47,60 @@
#include <vm/vm.h>
#include <vm/vm_kern.h>
+#include <machine/autoconf.h>
#include <machine/intr.h>
#include <machine/psl.h>
#include <machine/pio.h>
-unsigned int imen = 0xffffffff;
-volatile int cpl, ipending, astpending, tickspending;
-int imask[NIPL];
-u_char *interrupt_reg;
+#include <macppc/macppc/openpicreg.h>
#define NIRQ 32
+#define HWIRQ_MAX (NIRQ - 4 - 1)
+#define HWIRQ_MASK 0x0fffffff
void intr_calculatemasks __P((void));
char *intr_typename __P((int));
int fakeintr __P((void *));
-int intrtype[NIRQ], intrmask[NIRQ], intrlevel[NIRQ];
-struct intrhand *intrhand[NIRQ];
-
-extern u_int *heathrow_FCR;
-
static __inline int cntlzw __P((int));
static __inline int read_irq __P((void));
static __inline int mapirq __P((int));
static void enable_irq __P((int));
-static int hwirq[NIRQ], virq[ICU_LEN];
+static __inline u_int openpic_read __P((int));
+static __inline void openpic_write __P((int, u_int));
+void openpic_enable_irq __P((int));
+void openpic_disable_irq __P((int));
+void openpic_set_priority __P((int, int));
+static __inline int openpic_read_irq __P((int));
+static __inline void openpic_eoi __P((int));
+
+unsigned int imen = 0xffffffff;
+volatile int cpl, ipending, astpending, tickspending;
+int imask[NIPL];
+
+int intrtype[NIRQ], intrmask[NIRQ], intrlevel[NIRQ];
+struct intrhand *intrhand[NIRQ];
+
+static u_char hwirq[NIRQ], virq[ICU_LEN];
static int virq_max = 0;
-#define HWIRQ_MAX 27
-#define HWIRQ_MASK 0x0fffffff
+static u_char *obio_base, *openpic_base;
+
+extern u_int *heathrow_FCR;
+
+#define interrupt_reg (obio_base + 0x10)
-#define INT_STATE_REG0 (interrupt_reg + 0x20)
-#define INT_ENABLE_REG0 (interrupt_reg + 0x24)
-#define INT_CLEAR_REG0 (interrupt_reg + 0x28)
-#define INT_LEVEL_REG0 (interrupt_reg + 0x2c)
-#define INT_STATE_REG1 (INT_STATE_REG0 - 0x10)
-#define INT_ENABLE_REG1 (INT_ENABLE_REG0 - 0x10)
-#define INT_CLEAR_REG1 (INT_CLEAR_REG0 - 0x10)
-#define INT_LEVEL_REG1 (INT_LEVEL_REG0 - 0x10)
+#define INT_STATE_REG_H (interrupt_reg + 0x00)
+#define INT_ENABLE_REG_H (interrupt_reg + 0x04)
+#define INT_CLEAR_REG_H (interrupt_reg + 0x08)
+#define INT_LEVEL_REG_H (interrupt_reg + 0x0c)
+#define INT_STATE_REG_L (interrupt_reg + 0x10)
+#define INT_ENABLE_REG_L (interrupt_reg + 0x14)
+#define INT_CLEAR_REG_L (interrupt_reg + 0x18)
+#define INT_LEVEL_REG_L (interrupt_reg + 0x1c)
+
+#define have_openpic (openpic_base != NULL)
/*
* Map 64 irqs into 32 (bits).
@@ -129,28 +145,28 @@
read_irq()
{
int rv = 0;
- int state0, state1, p;
+ int lo, hi, p;
- state0 = in32rb(INT_STATE_REG0);
- if (state0)
- out32rb(INT_CLEAR_REG0, state0);
- while (state0) {
- p = 31 - cntlzw(state0);
+ lo = in32rb(INT_STATE_REG_L);
+ if (lo)
+ out32rb(INT_CLEAR_REG_L, lo);
+ while (lo) {
+ p = 31 - cntlzw(lo);
rv |= 1 << virq[p];
- state0 &= ~(1 << p);
+ lo &= ~(1 << p);
}
if (heathrow_FCR) /* has heathrow? */
- state1 = in32rb(INT_STATE_REG1);
+ hi = in32rb(INT_STATE_REG_H);
else
- state1 = 0;
+ hi = 0;
- if (state1)
- out32rb(INT_CLEAR_REG1, state1);
- while (state1) {
- p = 31 - cntlzw(state1);
+ if (hi)
+ out32rb(INT_CLEAR_REG_H, hi);
+ while (hi) {
+ p = 31 - cntlzw(hi);
rv |= 1 << virq[p + 32];
- state1 &= ~(1 << p);
+ hi &= ~(1 << p);
}
/* 1 << 0 is invalid. */
@@ -161,25 +177,93 @@
enable_irq(x)
int x;
{
- int state0, state1, v;
+ int lo, hi, v;
int irq;
x &= HWIRQ_MASK; /* XXX Higher bits are software interrupts. */
- state0 = state1 = 0;
+ lo = hi = 0;
while (x) {
v = 31 - cntlzw(x);
irq = hwirq[v];
if (irq < 32)
- state0 |= 1 << irq;
+ lo |= 1 << irq;
else
- state1 |= 1 << (irq - 32);
+ hi |= 1 << (irq - 32);
x &= ~(1 << v);
}
- out32rb(INT_ENABLE_REG0, state0);
+ out32rb(INT_ENABLE_REG_L, lo);
if (heathrow_FCR)
- out32rb(INT_ENABLE_REG1, state1);
+ out32rb(INT_ENABLE_REG_H, hi);
+}
+
+u_int
+openpic_read(reg)
+ int reg;
+{
+ char *addr = openpic_base + reg;
+
+ return in32rb(addr);
+}
+
+void
+openpic_write(reg, val)
+ int reg;
+ u_int val;
+{
+ char *addr = openpic_base + reg;
+
+ out32rb(addr, val);
+}
+
+void
+openpic_enable_irq(irq)
+ int irq;
+{
+ u_int x;
+
+ x = openpic_read(OPENPIC_SRC_VECTOR(irq));
+ x &= ~OPENPIC_IMASK;
+ openpic_write(OPENPIC_SRC_VECTOR(irq), x);
+}
+
+void
+openpic_disable_irq(irq)
+ int irq;
+{
+ u_int x;
+
+ x = openpic_read(OPENPIC_SRC_VECTOR(irq));
+ x |= OPENPIC_IMASK;
+ openpic_write(OPENPIC_SRC_VECTOR(irq), x);
+}
+
+void
+openpic_set_priority(cpu, pri)
+ int cpu, pri;
+{
+ u_int x;
+
+ x = openpic_read(OPENPIC_CPU_PRIORITY(cpu));
+ x &= ~OPENPIC_CPU_PRIORITY_MASK;
+ x |= pri;
+ openpic_write(OPENPIC_CPU_PRIORITY(cpu), x);
+}
+
+int
+openpic_read_irq(cpu)
+ int cpu;
+{
+ return openpic_read(OPENPIC_IACK(cpu)) & OPENPIC_VECTOR_MASK;
+}
+
+void
+openpic_eoi(cpu)
+ int cpu;
+{
+ openpic_write(OPENPIC_EOI(cpu), 0);
+ openpic_read(OPENPIC_EOI(cpu));
}
/*
@@ -192,6 +276,7 @@
intr_calculatemasks()
{
int irq, level;
+ int irqs = 0;
struct intrhand *q;
/* First, figure out which levels each IRQ uses. */
@@ -275,11 +360,18 @@
}
/* Lastly, determine which IRQs are actually in use. */
- {
- register int irqs = 0;
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