Source-Changes-HG archive
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]
[src/netbsd-1-5]: src/sys/dev/pci Pull up revisions 1.46, 1.48 (requested by f...
details: https://anonhg.NetBSD.org/src/rev/00b5c4c33c37
branches: netbsd-1-5
changeset: 491542:00b5c4c33c37
user: he <he%NetBSD.org@localhost>
date: Tue May 01 12:54:28 2001 +0000
description:
Pull up revisions 1.46,1.48 (requested by fvdl):
Deal correctly with 16-bit pcmcia cards. Fixes PR#12736 and
PR#12737.
diffstat:
sys/dev/pci/pccbb.c | 103 +++++++++++++++++++++++++++------------------------
1 files changed, 54 insertions(+), 49 deletions(-)
diffs (210 lines):
diff -r 4c549d8095ee -r 00b5c4c33c37 sys/dev/pci/pccbb.c
--- a/sys/dev/pci/pccbb.c Tue May 01 12:46:37 2001 +0000
+++ b/sys/dev/pci/pccbb.c Tue May 01 12:54:28 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pccbb.c,v 1.42.2.3 2000/12/15 00:22:39 he Exp $ */
+/* $NetBSD: pccbb.c,v 1.42.2.4 2001/05/01 12:54:28 he Exp $ */
/*
* Copyright (c) 1998, 1999 and 2000
@@ -755,8 +755,9 @@
/* Route functional interrupts to PCI. */
reg = pci_conf_read(pc, tag, PCI_BCR_INTR);
- reg &= ~CB_BCR_INTR_IREQ_ENABLE; /* use PCI Intr */
+ reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */
reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */
+ reg |= CB_BCR_RESET_ENABLE; /* assert reset */
pci_conf_write(pc, tag, PCI_BCR_INTR, reg);
switch (sc->sc_chipset) {
@@ -797,6 +798,15 @@
pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0);
pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff);
pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0);
+
+ /* reset 16-bit pcmcia bus */
+ bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh,
+ 0x800 + PCIC_INTR,
+ bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh,
+ 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET);
+
+ /* turn of power */
+ pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V);
}
@@ -841,7 +851,7 @@
* needs that while in PCMCIA mode.
* 4) Clear any pending CSC interrupt.
*/
- Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE | PCIC_INTR_RESET);
+ Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE);
if (sc->sc_chipset == CB_TI113X) {
Pcic_write(ph, PCIC_CSC_INTR, 0);
} else {
@@ -1071,6 +1081,9 @@
struct pcic_handle *ph;
int reg;
{
+ bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h,
+ PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ);
+
return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h,
PCCBB_PCMCIA_OFFSET + reg);
}
@@ -1083,6 +1096,9 @@
{
bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg,
val);
+
+ bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h,
+ PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE);
}
/*
@@ -1217,13 +1233,6 @@
bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl);
status = bus_space_read_4(memt, memh, CB_SOCKET_STAT);
- delay(20 * 1000); /* wait 20 ms: Vcc setup time */
- /*
- * XXX delay 200 ms: though the standard defines that the Vcc set-up
- * time is 20 ms, some PC-Card bridge requires longer duration.
- */
- delay(200 * 1000);
-
if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */
printf
("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n",
@@ -1263,6 +1272,13 @@
#endif
return 0;
}
+
+ /*
+ * XXX delay 300 ms: though the standard defines that the Vcc set-up
+ * time is 20 ms, some PC-Card bridge requires longer duration.
+ */
+ delay(300 * 1000);
+
return 1; /* power changed correctly */
}
@@ -1651,24 +1667,23 @@
void *arg;
{
struct pccbb_intrhand_list *pil, *newpil;
+ pcireg_t reg;
DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil));
if (sc->sc_pil == NULL) {
/* initialize bridge intr routing */
+ reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR);
+ reg &= ~CB_BCR_INTR_IREQ_ENABLE;
+ pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg);
switch (sc->sc_chipset) {
case CB_TI113X:
- {
- pcireg_t cbctrl =
- pci_conf_read(sc->sc_pc, sc->sc_tag,
- PCI_CBCTRL);
- /* functional intr enabled */
- cbctrl |= PCI113X_CBCTRL_PCI_INTR;
- pci_conf_write(sc->sc_pc, sc->sc_tag,
- PCI_CBCTRL, cbctrl);
- break;
- }
+ reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL);
+ /* functional intr enabled */
+ reg |= PCI113X_CBCTRL_PCI_INTR;
+ pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg);
+ break;
default:
break;
}
@@ -1713,6 +1728,7 @@
void *ih;
{
struct pccbb_intrhand_list *pil, **pil_prev;
+ pcireg_t reg;
DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil));
@@ -1733,18 +1749,18 @@
DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n"));
+ /* stop routing PCI intr */
+ reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR);
+ reg |= CB_BCR_INTR_IREQ_ENABLE;
+ pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg);
+
switch (sc->sc_chipset) {
case CB_TI113X:
- {
- pcireg_t cbctrl =
- pci_conf_read(sc->sc_pc, sc->sc_tag,
- PCI_CBCTRL);
- /* functional intr disabled */
- cbctrl &= ~PCI113X_CBCTRL_PCI_INTR;
- pci_conf_write(sc->sc_pc, sc->sc_tag,
- PCI_CBCTRL, cbctrl);
- break;
- }
+ reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL);
+ /* functional intr disabled */
+ reg &= ~PCI113X_CBCTRL_PCI_INTR;
+ pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg);
+ break;
default:
break;
}
@@ -2217,15 +2233,9 @@
return;
}
- /* assert reset bit */
- intr = Pcic_read(ph, PCIC_INTR);
- intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK);
- Pcic_write(ph, PCIC_INTR, intr);
-
/* disable socket i/o: negate output enable bit */
- power = Pcic_read(ph, PCIC_PWRCTL);
- power &= ~PCIC_PWRCTL_OE;
+ power = 0;
Pcic_write(ph, PCIC_PWRCTL, power);
/* power down the socket to reset it, clear the card reset pin */
@@ -2238,21 +2248,16 @@
*/
/* delay(300*1000); too much */
- /* power up the socket */
- pccbb_power(sc, voltage);
-
- /*
- * wait 100ms until power raise (Tpr) and 20ms to become
- * stable (Tsu(Vcc)).
- *
- * some machines require some more time to be settled
- * (another 200ms is added here).
- */
- /* delay((100 + 20 + 200)*1000); too much */
-
+ /* assert reset bit */
+ intr = Pcic_read(ph, PCIC_INTR);
+ intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK);
+ Pcic_write(ph, PCIC_INTR, intr);
+
+ /* power up the socket and output enable */
power = Pcic_read(ph, PCIC_PWRCTL);
power |= PCIC_PWRCTL_OE;
Pcic_write(ph, PCIC_PWRCTL, power);
+ pccbb_power(sc, voltage);
/*
* hold RESET at least 10us.
Home |
Main Index |
Thread Index |
Old Index