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[src/trunk]: src/sys/arch/mips MachForceCacheUpdate and cacheflush_bug have n...
details: https://anonhg.NetBSD.org/src/rev/3715a7e70d19
branches: trunk
changeset: 486481:3715a7e70d19
user: soren <soren%NetBSD.org@localhost>
date: Tue May 23 04:21:39 2000 +0000
description:
MachForceCacheUpdate and cacheflush_bug have never been used in NetBSD,
so remove references them, and do a little other cleanup.
diffstat:
sys/arch/mips/conf/files.mips | 4 +++-
sys/arch/mips/include/cpuregs.h | 5 +----
sys/arch/mips/include/locore.h | 14 ++------------
sys/arch/mips/include/r3900regs.h | 4 +---
sys/arch/mips/mips/locore_mips3.S | 25 +++++--------------------
sys/arch/mips/mips/mem.c | 5 ++++-
sys/arch/mips/mips/mips_machdep.c | 29 +++++------------------------
7 files changed, 21 insertions(+), 65 deletions(-)
diffs (truncated from 329 to 300 lines):
diff -r 309613605bcf -r 3715a7e70d19 sys/arch/mips/conf/files.mips
--- a/sys/arch/mips/conf/files.mips Tue May 23 03:50:12 2000 +0000
+++ b/sys/arch/mips/conf/files.mips Tue May 23 04:21:39 2000 +0000
@@ -1,9 +1,11 @@
-# $NetBSD: files.mips,v 1.25 2000/05/21 03:31:35 soren Exp $
+# $NetBSD: files.mips,v 1.26 2000/05/23 04:21:39 soren Exp $
#
defopt opt_cputype.h NOTYET # MIPS1 MIPS3 MIPS4 NOFPU
# MIPS3_4100 MIPS3_5200
# ENABLE_MIPS_TX3900
+ # ENABLE_MIPS_R4700
+ # ENABLE_MIPS_R3NKK
defopt opt_mips_cache.h MIPS3_L2CACHE_ABSENT
MIPS3_L2CACHE_PRESENT
file arch/mips/mips/db_disasm.c ddb
diff -r 309613605bcf -r 3715a7e70d19 sys/arch/mips/include/cpuregs.h
--- a/sys/arch/mips/include/cpuregs.h Tue May 23 03:50:12 2000 +0000
+++ b/sys/arch/mips/include/cpuregs.h Tue May 23 04:21:39 2000 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuregs.h,v 1.31 2000/05/21 04:03:35 soren Exp $ */
+/* $NetBSD: cpuregs.h,v 1.32 2000/05/23 04:21:39 soren Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -576,9 +576,6 @@
/*
* Patch codes to hide CPU design differences between MIPS1 and MIPS3.
- *
- * XXX INT_MASK and HARD_INT_MASK are here only because we dont
- * support the mips3 on-chip timer which is tied to INT_5.
*/
#if !defined(MIPS3) && defined(MIPS1)
diff -r 309613605bcf -r 3715a7e70d19 sys/arch/mips/include/locore.h
--- a/sys/arch/mips/include/locore.h Tue May 23 03:50:12 2000 +0000
+++ b/sys/arch/mips/include/locore.h Tue May 23 04:21:39 2000 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.h,v 1.32 2000/05/21 03:23:15 soren Exp $ */
+/* $NetBSD: locore.h,v 1.33 2000/05/23 04:21:40 soren Exp $ */
/*
* Copyright 1996 The Board of Trustees of The Leland Stanford
@@ -23,15 +23,11 @@
* MachFlushCache
* MachFlushDCache
* MachFlushICache
- * MachForceCacheUpdate
* wbflush
* proc_trampoline()
* cpu_switch_resume()
*
- * We currently provide support for:
- *
- * r2000 and r3000 (mips ISA-I)
- * r4000 and r4400 in 32-bit mode (mips ISA-III?)
+ * We currently provide support for MIPS I and MIPS III.
*/
#ifndef _MIPS_LOCORE_H
@@ -54,7 +50,6 @@
void mips1_FlushCache __P((void));
void mips1_FlushDCache __P((vaddr_t addr, vsize_t len));
void mips1_FlushICache __P((vaddr_t addr, vsize_t len));
-void mips1_ForceCacheUpdate __P((void));
void mips1_SetPID __P((int pid));
void mips1_TBIA __P((int));
@@ -71,7 +66,6 @@
void mips3_FlushCache __P((void));
void mips3_FlushDCache __P((vaddr_t addr, vaddr_t len));
void mips3_FlushICache __P((vaddr_t addr, vaddr_t len));
-void mips3_ForceCacheUpdate __P((void));
void mips3_HitFlushDCache __P((vaddr_t, int));
void mips3_SetPID __P((int pid));
@@ -115,7 +109,6 @@
void (*flushCache) __P((void));
void (*flushDCache) __P((vaddr_t addr, vsize_t len));
void (*flushICache) __P((vaddr_t addr, vsize_t len));
- void (*forceCacheUpdate) __P((void));
void (*setTLBpid) __P((int pid));
void (*TBIAP) __P((int));
void (*TBIS) __P((vaddr_t));
@@ -160,7 +153,6 @@
#define MachHitFlushDCache mips3_HitFlushDCache
#define MachFlushICache mips3_FlushICache
#endif
-#define MachForceCacheUpdate mips3_ForceCacheUpdate
#define MachSetPID mips3_SetPID
#define MIPS_TBIAP() mips3_TBIAP(mips_num_tlb_entries)
#define MIPS_TBIS mips3_TBIS
@@ -174,7 +166,6 @@
#define MachFlushCache mips1_FlushCache
#define MachFlushDCache mips1_FlushDCache
#define MachFlushICache mips1_FlushICache
-#define MachForceCacheUpdate mips1_ForceCacheUpdate
#define MachSetPID mips1_SetPID
#define MIPS_TBIAP() mips1_TBIAP(mips_num_tlb_entries)
#define MIPS_TBIS mips1_TBIS
@@ -190,7 +181,6 @@
#define MachFlushCache (*(mips_locore_jumpvec.flushCache))
#define MachFlushDCache (*(mips_locore_jumpvec.flushDCache))
#define MachFlushICache (*(mips_locore_jumpvec.flushICache))
-#define MachForceCacheUpdate (*(mips_locore_jumpvec.forceCacheUpdate))
#define MachSetPID (*(mips_locore_jumpvec.setTLBpid))
#define MIPS_TBIAP() (*(mips_locore_jumpvec.TBIAP))(mips_num_tlb_entries)
#define MIPS_TBIS (*(mips_locore_jumpvec.TBIS))
diff -r 309613605bcf -r 3715a7e70d19 sys/arch/mips/include/r3900regs.h
--- a/sys/arch/mips/include/r3900regs.h Tue May 23 03:50:12 2000 +0000
+++ b/sys/arch/mips/include/r3900regs.h Tue May 23 04:21:39 2000 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: r3900regs.h,v 1.1 1999/11/29 11:13:11 uch Exp $ */
+/* $NetBSD: r3900regs.h,v 1.2 2000/05/23 04:21:40 soren Exp $ */
/*
* Copyright (c) 1999, by UCHIYAMA Yasushi
@@ -138,5 +138,3 @@
#define CPUREG_A0 4
#define CPUREG_T0 8
-
-
diff -r 309613605bcf -r 3715a7e70d19 sys/arch/mips/mips/locore_mips3.S
--- a/sys/arch/mips/mips/locore_mips3.S Tue May 23 03:50:12 2000 +0000
+++ b/sys/arch/mips/mips/locore_mips3.S Tue May 23 04:21:39 2000 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: locore_mips3.S,v 1.29 2000/05/21 03:23:16 soren Exp $ */
+/* $NetBSD: locore_mips3.S,v 1.30 2000/05/23 04:21:40 soren Exp $ */
/*
* Copyright (c) 1997 Jonathan Stone (hereinafter referred to as the author)
@@ -1447,18 +1447,6 @@
sw t5, 12(a1)
END(mips3_TLBRead)
-
-/*----------------------------------------------------------------------------
- *
- * R4000 cache flushing code.
- *
- *----------------------------------------------------------------------------
- */
-
-/*
- * XXX need to handle two-way caches for r4600 and mips ISA-IV.
- */
-
/*----------------------------------------------------------------------------
*
* mips3_FlushCache --
@@ -2002,7 +1990,7 @@
* mips3_VCED --
*
* Handle virtual coherency exceptions.
- * Called directly from the mips3 execption-table code.
+ * Called directly from the mips3 execption-table code.
* only k0, k1 are avaiable on entry
*
* Results:
@@ -2516,7 +2504,7 @@
* each time the COUNT register increments past the COMPARE register.
*
* (The mips interrupt mask defintions currently leaves this interrupt
- * unconditionally masked out on mips3 CPUs.)
+ * unconditionally masked out on mips3 CPUs.)
*/
LEAF(mips3_read_compare)
mfc0 v0, MIPS_COP_0_COMPARE
@@ -2607,7 +2595,7 @@
/*
* The variables below are used to communicate the cache handling
- * to higher-level software.
+ * to higher-level software.
*/
.sdata
@@ -2615,11 +2603,8 @@
_C_LABEL(mips3_L1TwoWayCache):
.word 0
- .globl _C_LABEL(mips3_cacheflush_bug)
-_C_LABEL(mips3_cacheflush_bug):
- .word 0
+ .data
- .data
.globl _C_LABEL(mips3_locoresw)
_C_LABEL(mips3_locoresw):
.word _C_LABEL(mips3_cpu_switch_resume)
diff -r 309613605bcf -r 3715a7e70d19 sys/arch/mips/mips/mem.c
--- a/sys/arch/mips/mips/mem.c Tue May 23 03:50:12 2000 +0000
+++ b/sys/arch/mips/mips/mem.c Tue May 23 04:21:39 2000 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: mem.c,v 1.20 2000/03/03 02:33:21 castor Exp $ */
+/* $NetBSD: mem.c,v 1.21 2000/05/23 04:21:40 soren Exp $ */
/*
* Copyright (c) 1988 University of Utah.
@@ -114,6 +114,9 @@
case 0:
v = uio->uio_offset;
c = iov->iov_len;
+ /*
+ * XXX Broken; assumes contiguous physical memory.
+ */
if (v + c > ctob(physmem))
return (EFAULT);
v += MIPS_KSEG0_START;
diff -r 309613605bcf -r 3715a7e70d19 sys/arch/mips/mips/mips_machdep.c
--- a/sys/arch/mips/mips/mips_machdep.c Tue May 23 03:50:12 2000 +0000
+++ b/sys/arch/mips/mips/mips_machdep.c Tue May 23 04:21:39 2000 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: mips_machdep.c,v 1.80 2000/05/21 04:25:57 soren Exp $ */
+/* $NetBSD: mips_machdep.c,v 1.81 2000/05/23 04:21:40 soren Exp $ */
/*-
* Copyright (c) 1998 The NetBSD Foundation, Inc.
@@ -52,7 +52,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.80 2000/05/21 04:25:57 soren Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.81 2000/05/23 04:21:40 soren Exp $");
#include "opt_compat_netbsd.h"
#include "opt_compat_ultrix.h"
@@ -129,14 +129,13 @@
int r3900_icache_direct;
#endif
/*
- * MIPS-I (r2000 and r3000) locore-function vector.
+ * MIPS-I locore function vector
*/
mips_locore_jumpvec_t mips1_locore_vec =
{
mips1_FlushCache,
mips1_FlushDCache,
mips1_FlushICache,
- /*mips1_FlushICache*/ mips1_FlushCache,
mips1_SetPID,
mips1_TBIAP,
mips1_TBIS,
@@ -178,21 +177,13 @@
#ifdef MIPS3
/*
- * MIPS-III (r4000) locore-function vector.
+ * MIPS III locore function vector
*/
mips_locore_jumpvec_t mips3_locore_vec =
{
mips3_FlushCache,
mips3_FlushDCache,
mips3_FlushICache,
-#if 0
- /*
- * No such vector exists, perhaps it was meant to be HitFlushDCache?
- */
- mips3_ForceCacheUpdate,
-#else
- mips3_FlushCache,
-#endif
mips3_SetPID,
mips3_TBIAP,
mips3_TBIS,
@@ -331,7 +322,7 @@
* variable cpu_id, into which the kernel locore start code
* writes the cpu ID register, and to then copy appropriate
* cod into the CPU exception-vector entries and the jump tables
- * used to hide the differences in cache and TLB handling in
+ * used to hide the differences in cache and TLB handling in
* different MIPS CPUs.
*
* This should be the very first thing called by each port's
@@ -388,36 +379,28 @@
cpu_arch = 3;
mips_num_tlb_entries = MIPS3_TLB_NUM_TLB_ENTRIES;
mips3_L1TwoWayCache = 0;
- mips3_cacheflush_bug = 0;
-#if 1 /* XXX FIXME: avoid hangs in mips3_vector_init() */
- mips3_cacheflush_bug = 1;
-#endif
break;
case MIPS_R4100:
cpu_arch = 3;
mips_num_tlb_entries = 32;
mips3_L1TwoWayCache = 0;
- mips3_cacheflush_bug = 0;
break;
case MIPS_R4300:
cpu_arch = 3;
mips_num_tlb_entries = MIPS_R4300_TLB_NUM_TLB_ENTRIES;
mips3_L1TwoWayCache = 0;
- mips3_cacheflush_bug = 0;
break;
case MIPS_R4600:
cpu_arch = 3;
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