[src/trunk]: src/sys/arch/hpcmips/vr - show bus clock freq setting and memory...

[sato <sato%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/8adaceead675
branches:  trunk
changeset: 481366:8adaceead675
user:      sato <sato%NetBSD.org@localhost>
date:      Thu Jan 27 06:25:54 2000 +0000

description:
- show bus clock freq setting and memory clock freq setting in boot time.

diffstat:

 sys/arch/hpcmips/vr/bcu_vrip.c |  82 +++++++++++++++++++++++++++++++++++++++++-
 sys/arch/hpcmips/vr/bcureg.h   |  28 +++++++++++--
 2 files changed, 104 insertions(+), 6 deletions(-)

diffs (146 lines):

diff -r 03a47d6fec19 -r 8adaceead675 sys/arch/hpcmips/vr/bcu_vrip.c
--- a/sys/arch/hpcmips/vr/bcu_vrip.c    Thu Jan 27 06:23:05 2000 +0000
+++ b/sys/arch/hpcmips/vr/bcu_vrip.c    Thu Jan 27 06:25:54 2000 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: bcu_vrip.c,v 1.4 1999/12/16 12:10:02 shin Exp $        */
+/*     $NetBSD: bcu_vrip.c,v 1.5 2000/01/27 06:25:54 sato Exp $        */
 
 /*-
  * Copyright (c) 1999 SATO Kazumi. All rights reserved.
@@ -55,6 +55,8 @@
 static void vrbcu_write __P((struct vrbcu_softc *, int, unsigned short));
 static unsigned short vrbcu_read __P((struct vrbcu_softc *, int));
 
+static void vrbcu_dump_regs __P((void));
+
 char   *vr_cpuname=NULL;
 int    vr_major=-1;
 int    vr_minor=-1;
@@ -108,6 +110,84 @@
 
        printf("\n");
        the_bcu_sc = sc;
+       vrbcu_dump_regs();
+}
+
+static void
+vrbcu_dump_regs()
+{
+       struct vrbcu_softc *sc = the_bcu_sc;
+       int reg;
+       int cpuclock, tclock, vtclock, cpuid, vt;
+
+#ifdef VRBCUDEBUG
+       reg = vrbcu_read(sc, BCUCNT1_REG_W);
+       printf("vrbcu: CNT1 %x: ",  reg);
+       bitdisp16(reg);
+       reg = vrbcu_read(sc, BCUCNT2_REG_W);
+       printf("vrbcu: CNT2 %x: ",  reg);
+       bitdisp16(reg);
+       reg = vrbcu_read(sc, BCUSPEED_REG_W);
+       printf("vrbcu: SPEED %x: ",  reg);
+       bitdisp16(reg);
+       reg = vrbcu_read(sc, BCUERRST_REG_W);
+       printf("vrbcu: ERRST %x: ",  reg);
+       bitdisp16(reg);
+       reg = vrbcu_read(sc, BCURFCNT_REG_W);
+       printf("vrbcu: RFCNT %x\n",  reg);
+       reg = vrbcu_read(sc, BCUREFCOUNT_REG_W);
+       printf("vrbcu: RFCOUNT %x\n",  reg);
+#endif /* VRBCUDEBUG */        
+       reg = vrbcu_read(sc, BCUCLKSPEED_REG_W);
+#ifdef VRBCUDEBUG
+       printf("vrbcu: CLKSPEED %x: \n",  reg);
+#endif /* VRBCUDEBUG */        
+       cpuclock = vrbcu_vrip_getcpuclock();
+       cpuid = vrbcu_vrip_getcpuid();
+
+       switch (cpuid) {
+       case BCUREVID_RID_4101:
+               /* assume 33MHz */
+               vtclock = tclock = cpuclock/2;  /* XXX */
+               break;
+       case BCUREVID_RID_4102:
+               vtclock = tclock = cpuclock/2;
+               break;
+       case BCUREVID_RID_4111:
+               if ((reg&BCUCLKSPEED_DIVT2B) == 0) 
+                       vtclock = tclock = cpuclock/2;
+               else if ((reg&BCUCLKSPEED_DIVT3B) == 0) 
+                       vtclock = tclock = cpuclock/3;
+               else if ((reg&BCUCLKSPEED_DIVT4B) == 0) 
+                       vtclock = tclock = cpuclock/4;
+               else
+                       vtclock = tclock = 0; /* XXX */
+               break;
+       case BCUREVID_RID_4121:
+                       tclock = cpuclock / ((reg&BCUCLKSPEED_DIVTMASK)>>BCUCLKSPEED_DIVTSHFT);
+                       vt = ((reg&BCUCLKSPEED_DIVVTMASK)>>BCUCLKSPEED_DIVVTSHFT);
+                       if (vt == 0)
+                               vtclock = 0; /* XXX */
+                       else if (vt < 0x9)
+                               vtclock = cpuclock / vt;
+                       else
+                               vtclock = cpuclock / ((vt - 8)*2+1) * 2;
+               break;
+       default:
+               break;
+       }
+       printf("vrbcu: cpu %d.%03dMHz, bus %d.%03dMHz, ram %d.%03dMHz\n",
+               cpuclock/1000000, (cpuclock%1000000)/1000,
+               tclock/1000000, (tclock%1000000)/1000,
+               vtclock/1000000, (vtclock%1000000)/1000);
+#ifdef VRBCUDEBUG
+       if (cpuid >= BCUREVID_RID_4111) {
+               reg = vrbcu_read(sc, BCUCNT3_REG_W);
+               printf("vrbcu: CNT3 %x: ",  reg);
+               bitdisp16(reg);
+       }
+#endif /* VRBCUDEBUG */
+
 }
 
 static char *cpuname[] = {
diff -r 03a47d6fec19 -r 8adaceead675 sys/arch/hpcmips/vr/bcureg.h
--- a/sys/arch/hpcmips/vr/bcureg.h      Thu Jan 27 06:23:05 2000 +0000
+++ b/sys/arch/hpcmips/vr/bcureg.h      Thu Jan 27 06:25:54 2000 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: bcureg.h,v 1.2 1999/12/13 03:11:36 sato Exp $  */
+/*     $NetBSD: bcureg.h,v 1.3 2000/01/27 06:25:54 sato Exp $  */
 
 /*-
  * Copyright (c) 1999 SATO Kazumi. All rights reserved.
@@ -173,11 +173,29 @@
 
 #define        BCUCLKSPEED_REG_W       0x014   /* Clock Speed Register */
 
-#define                BCUCLKSPEED_DIV2B       (1<<15)
-#define                BCUCLKSPEED_DIV3B       (1<<14)
-#define                BCUCLKSPEED_DIV4B       (1<<13)
+#define                BCUCLKSPEED_DIVT2B      (1<<15)         /* (= vr4102, vr4111) */
+#define                BCUCLKSPEED_DIVT3B      (1<<14)         /* (= vr4111) */
+#define                BCUCLKSPEED_DIVT4B      (1<<13)         /* (= vr4111) */
+
+#define                BCUCLKSPEED_DIVTMASK    (0xf<<12)       /* (= vr4121) */
+#define                        BCUCLKSPEED_DIVT3       0x3
+#define                        BCUCLKSPEED_DIVT4       0x4
+#define                        BCUCLKSPEED_DIVT5       0x5
+#define                        BCUCLKSPEED_DIVT6       0x6
+#define                BCUCLKSPEED_DIVTSHFT    (12)            
 
-#define                BCUCLKSPEED_CLKSPMASK   (0xf)           /* calculate for Clock */
+#define                BCUCLKSPEED_DIVVTMASK   (0xf<<8)        /* (= vr4121) */
+#define                        BCUCLKSPEED_DIVVT1      0x1
+#define                        BCUCLKSPEED_DIVVT2      0x2
+#define                        BCUCLKSPEED_DIVVT3      0x3
+#define                        BCUCLKSPEED_DIVVT4      0x4
+#define                        BCUCLKSPEED_DIVVT5      0x5
+#define                        BCUCLKSPEED_DIVVT6      0x6
+#define                        BCUCLKSPEED_DIVVT1_5    0x9
+#define                        BCUCLKSPEED_DIVVT2_5    0xa
+#define                BCUCLKSPEED_DIVVTSHFT   (8)             
+
+#define                BCUCLKSPEED_CLKSPMASK   (0x1f)          /* calculate for Clock */
 #define                BCUCLKSPEED_CLKSPSHFT   (0)             
 
 #define        BCUCNT3_REG_W           0x016   /* BCU Control Register 3 (>= vr4111) */