[src/trunk]: src/sys/arch/hpcmips/hpcmips clear CPU count register interrupt ...

[shin <shin%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/5511c363a079
branches:  trunk
changeset: 486146:5511c363a079
user:      shin <shin%NetBSD.org@localhost>
date:      Sun May 14 03:16:11 2000 +0000

description:
clear CPU count register interrupt properly (VR4100).

diffstat:

 sys/arch/hpcmips/hpcmips/machdep.c |  10 +++++-----
 1 files changed, 5 insertions(+), 5 deletions(-)

diffs (37 lines):

diff -r 9e7da62ff36b -r 5511c363a079 sys/arch/hpcmips/hpcmips/machdep.c
--- a/sys/arch/hpcmips/hpcmips/machdep.c        Sun May 14 02:31:02 2000 +0000
+++ b/sys/arch/hpcmips/hpcmips/machdep.c        Sun May 14 03:16:11 2000 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: machdep.c,v 1.24 2000/05/09 13:20:55 shin Exp $        */
+/*     $NetBSD: machdep.c,v 1.25 2000/05/14 03:16:11 shin Exp $        */
 
 /*
  * Copyright (c) 1988 University of Utah.
@@ -43,7 +43,7 @@
 
 #include <sys/cdefs.h>                 /* RCS ID & Copyright macro defns */
 
-__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.24 2000/05/09 13:20:55 shin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.25 2000/05/14 03:16:11 shin Exp $");
 
 /* from: Utah Hdr: machdep.c 1.63 91/04/24 */
 #include "opt_vr41x1.h"
@@ -731,15 +731,15 @@
 {
        uvmexp.intrs++;
 
-#if defined(MIPS3) && defined(MIPS_INT_MASK_CLOCK)
-       if (ipending & MIPS_INT_MASK_CLOCK) {
+#ifdef VR41X1
+       if (ipending & MIPS_INT_MASK_5) {
                /*
                 *  Writing a value to the Compare register,
                 *  as a side effect, clears the timer interrupt request.
                 */
                mips3_write_compare(mips3_cycle_count());
        }
-#endif /* MIPS3 && MIPS_INT_MASK_CLOCK */
+#endif
 
        /* device interrupts */
 #ifdef ENABLE_MIPS_TX3900