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[src/netbsd-1-5]: src/sys/arch/mips/mips Pull up rev 1.37: Fix pasto.
details: https://anonhg.NetBSD.org/src/rev/2908cf512019
branches: netbsd-1-5
changeset: 488210:2908cf512019
user: soren <soren%NetBSD.org@localhost>
date: Wed Jun 21 19:42:06 2000 +0000
description:
Pull up rev 1.37: Fix pasto.
diffstat:
sys/arch/mips/mips/locore_mips3.S | 2698 +++++++++++++++++++++++++++++++++++++
1 files changed, 2698 insertions(+), 0 deletions(-)
diffs (truncated from 2702 to 300 lines):
diff -r dda5e4d3caee -r 2908cf512019 sys/arch/mips/mips/locore_mips3.S
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/mips/mips/locore_mips3.S Wed Jun 21 19:42:06 2000 +0000
@@ -0,0 +1,2698 @@
+/* $NetBSD: locore_mips3.S,v 1.36.2.2 2000/06/21 19:42:06 soren Exp $ */
+
+/*
+ * Copyright (c) 1997 Jonathan Stone (hereinafter referred to as the author)
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Jonathan R. Stone for
+ * the NetBSD Project.
+ * 4. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * Copyright (c) 1992, 1993
+ * The Regents of the University of California. All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * Digital Equipment Corporation and Ralph Campbell.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the University of
+ * California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Copyright (C) 1989 Digital Equipment Corporation.
+ * Permission to use, copy, modify, and distribute this software and
+ * its documentation for any purpose and without fee is hereby granted,
+ * provided that the above copyright notice appears in all copies.
+ * Digital Equipment Corporation makes no representations about the
+ * suitability of this software for any purpose. It is provided "as is"
+ * without express or implied warranty.
+ *
+ * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/loMem.s,
+ * v 1.1 89/07/11 17:55:04 nelson Exp SPRITE (DECWRL)
+ * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAsm.s,
+ * v 9.2 90/01/29 18:00:39 shirriff Exp SPRITE (DECWRL)
+ * from: Header: /sprite/src/kernel/vm/ds3100.md/vmPmaxAsm.s,
+ * v 1.1 89/07/10 14:27:41 nelson Exp SPRITE (DECWRL)
+ *
+ * @(#)locore.s 8.5 (Berkeley) 1/4/94
+ */
+#include "opt_cputype.h"
+#include "opt_ddb.h"
+
+#include <sys/cdefs.h>
+
+#include <mips/asm.h>
+#include <mips/cpuregs.h>
+#include <machine/param.h>
+#include <machine/endian.h>
+
+#include "assym.h"
+
+/*
+ * XXX We need a cleaner way of handling the instruction hazards of
+ * the various processors. Here are the relevant rules for the QED 52XX:
+ * tlbw[ri] -- two integer ops beforehand
+ * tlbr -- two integer ops beforehand
+ * tlbp -- two integer ops beforehand
+ * mtc0 [PageMask,EntryHi,Cp0] -- two integer ops afterwards
+ * changing JTLB -- two integer ops afterwards
+ * mtc0 [EPC,ErrorEPC,Status] -- two int ops afterwards before eret
+ * config.k0 -- five int ops before kseg0, ckseg0 memref
+ *
+ * For the IDT R4000, some hazards are:
+ * mtc0/mfc0 one integer op before and after
+ * tlbp -- one integer op afterwards
+ * Obvious solution is to take least common denominator.
+ */
+
+/*
+ * XXX mips/include
+ */
+#define C_IINV_I 0x00
+#define C_IWBINV_D 0x01
+#define C_IINV_SI 0x02
+#define C_IWBINV_SD 0x03
+
+#define C_ILDTAG_I 0x04
+#define C_ILDTAG_D 0x05
+#define C_ILDTAG_SI 0x06
+#define C_ILDTAG_SD 0x07
+
+#define C_HINV_I 0x10
+#define C_HINV_D 0x11
+#define C_HINV_SI 0x12
+#define C_HINV_SD 0x13
+
+#define C_HWBINV_D 0x15
+#define C_HWBINV_SD 0x17
+
+#define C_HSETV_SI 0x1e
+#define C_HSETV_SD 0x1f
+
+/*
+ *============================================================================
+ *
+ * MIPS III ISA support, part 1: locore exception vectors.
+ * The following code is copied to the vector locations to which
+ * the CPU jumps in response to an exception or a TLB miss.
+ *
+ *============================================================================
+ */
+ .set noreorder
+ .set mips3
+ .text
+
+/*
+ *----------------------------------------------------------------------------
+ *
+ * mips3_TLBMiss --
+ *
+ * Vector code for the TLB-miss exception vector 0x80000000
+ * on an r4000.
+ *
+ * This code is copied to the TLB exception vector address to
+ * handle TLB translation misses.
+ * NOTE: This code should be relocatable and max 32 instructions!!!
+ *
+ * Don't check for invalid pte's here. We load them as well and
+ * let the processor trap to load the correct value after service.
+ *
+ * NOTE: This relies on a non-standard use of the XContext register. The
+ * upper 32 bits of the XContext register is loaded with the 32-bit address
+ * of the user PT segment table. This eliminatees the need to load the
+ * address of the segment table from memory on each miss.
+ * Also, the BadVAddr register contains the virtual address that caused the
+ * TLBmiss - the 32-bit address is signed extended to 64 bits in the BadVAddr
+ * register, so the upper 32 bits will be the same as bit 31 of the virtual
+ * address and is used to check for a user or kernel address.
+ *
+ *----------------------------------------------------------------------------
+ */
+VECTOR(mips3_TLBMiss, unknown)
+ .set noat
+ dmfc0 k0, MIPS_COP_0_BAD_VADDR # get the virtual address
+ dmfc0 k1, MIPS_COP_0_TLB_XCONTEXT
+ bltz k0, 4f # Kernel address (KSEG) if bit 31 set
+ srl k0, k0, SEGSHIFT - 2 # compute segment table index
+ and k0, k0, 0x7fc # index of segment table
+ dsra k1, k1, 32 # Tricky -- The lower bit is
+ # actually part of KSU but we must
+ # be a user address
+ add k1, k0, k1
+ lw k1, 0(k1)
+ dmfc0 k0, MIPS_COP_0_BAD_VADDR # get the virtual address
+ beq k1, zero, 5f # invalid segment map
+ srl k0, k0, PGSHIFT - 2 # compute segment map index
+ and k0, k0, ((NPTEPG/2) - 1) << 3
+ addu k1, k1, k0 # index into segment map
+ ld k0, 0(k1) # load both 32 bit pte's at once
+3: dsll k1, k0, 34 # Clear soft wired, ro bits
+ dsrl k1, k1, 34
+#if BYTE_ORDER == BIG_ENDIAN
+ dmtc0 k1, MIPS_COP_0_TLB_LO1
+ dsll k0, k0, 2
+ dsrl k0, k0, 34
+ dmtc0 k0, MIPS_COP_0_TLB_LO0
+#else
+ dmtc0 k1, MIPS_COP_0_TLB_LO0
+ dsll k0, k0, 2
+ dsrl k0, k0, 34
+ dmtc0 k0, MIPS_COP_0_TLB_LO1
+#endif
+ nop
+ nop # required for QED5230
+ tlbwr # update TLB
+ nop
+ nop
+ nop
+ nop
+ eret
+4:
+ j _C_LABEL(mips3_TLBMissException)
+ nop
+5:
+ j mips3_SlowFault
+ nop
+VECTOR_END(mips3_TLBMiss)
+
+/*
+ * mips3_XTLBMiss routine
+ *
+ * Vector code for the TLB-miss exception vector 0x80000080 on an r4000.
+ *
+ * This code is copied to the XTLB exception vector address to
+ * handle TLB translation misses while in 64-bit mode.
+ * NOTE: This code should be relocatable and max 32 instructions!!!
+ *
+ * Note that we do not support the full size of the PTEs, relying
+ * on appropriate truncation/sign extension.
+ *
+ * Don't check for invalid pte's here. We load them as well and
+ * let the processor trap to load the correct value after service.
+ *
+ * NOTE: This also relies on a non-standard use of the XContext register. The
+ * upper 32 bits of the XContext register is loaded with the 32-bit address
+ * of the user PT segment table. This eliminatees the need to load the
+ * address of the segment table from memory on each miss. The 32-bit address
+ * is shifted to form the 64-bit address, and will be a KSEG0 compatibility
+ * mode address (tricky!).
+ * Bit 63 in the BadVAddr register will be 0 for a user address, 1 for
+ * a kernel address.
+ */
+VECTOR(mips3_XTLBMiss, unknown)
+ dmfc0 k0, MIPS_COP_0_BAD_VADDR # get the virtual address
+ dmfc0 k1, MIPS_COP_0_TLB_XCONTEXT
+ bltz k0, 4f # Kernel address if bit 63 set.
+ srl k0, k0, SEGSHIFT - 2 # compute segment table index
+ and k0, k0, 0x7fc # index of segment table
+ dsra k1, k1, 32 # Tricky -- The lower bit is
+ # actually part of KSU but we must
+ # be a user address
+ add k1, k0, k1
+ lw k1, 0(k1)
+ dmfc0 k0, MIPS_COP_0_BAD_VADDR # get the virtual address
+ beq k1, zero, 5f # invalid segment map
+ srl k0, k0, PGSHIFT - 2 # compute segment map index
+ and k0, k0, ((NPTEPG/2) - 1) << 3
+ addu k1, k1, k0 # index into segment map
+ ld k0, 0(k1) # load both 32 bit pte's at once
+3: dsll k1, k0, 34 # Clear soft wired, ro bits
+ dsrl k1, k1, 34
+#if BYTE_ORDER == _BIG_ENDIAN
+ dmtc0 k1, MIPS_COP_0_TLB_LO1
+ dsll k0, k0, 2
+ dsrl k0, k0, 34
+ dmtc0 k0, MIPS_COP_0_TLB_LO0
+#else
+ dmtc0 k1, MIPS_COP_0_TLB_LO0
+ dsll k0, k0, 2
+ dsrl k0, k0, 34
+ dmtc0 k0, MIPS_COP_0_TLB_LO1
+#endif
+ nop
+ nop # required for QED5230
+ tlbwr # update TLB
+ nop
+ nop
+ nop
+ nop
+ eret
+4:
+ j mips3_TLBMissException
+ nop
+5:
+ j mips3_SlowFault
+ nop
+VECTOR_END(mips3_XTLBMiss)
+
+ .set at
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