Source-Changes-HG archive
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]
[src/trunk]: src/sys/arch/sparc/dev Use bus_space(9) functions to access the ...
details: https://anonhg.NetBSD.org/src/rev/48cb1920f382
branches: trunk
changeset: 480680:48cb1920f382
user: pk <pk%NetBSD.org@localhost>
date: Mon Jan 17 16:57:15 2000 +0000
description:
Use bus_space(9) functions to access the controller registers.
Add probes to the attach routines before poking the chip to see
where the registers are located.
diffstat:
sys/arch/sparc/dev/fd.c | 314 +++++++++++++++++++++++++++++---------------
sys/arch/sparc/dev/fdreg.h | 45 ++---
sys/arch/sparc/dev/fdvar.h | 11 +-
3 files changed, 229 insertions(+), 141 deletions(-)
diffs (truncated from 664 to 300 lines):
diff -r f358798ab011 -r 48cb1920f382 sys/arch/sparc/dev/fd.c
--- a/sys/arch/sparc/dev/fd.c Mon Jan 17 16:53:18 2000 +0000
+++ b/sys/arch/sparc/dev/fd.c Mon Jan 17 16:57:15 2000 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: fd.c,v 1.69 2000/01/11 12:59:45 pk Exp $ */
+/* $NetBSD: fd.c,v 1.70 2000/01/17 16:57:15 pk Exp $ */
/*-
* Copyright (c) 1993, 1994, 1995 Charles M. Hannum.
@@ -111,7 +111,7 @@
struct fdc_softc {
struct device sc_dev; /* boilerplate */
bus_space_tag_t sc_bustag;
- caddr_t sc_reg;
+
struct fd_softc *sc_fd[4]; /* pointers to children */
TAILQ_HEAD(drivehead, fd_softc) sc_drives;
enum fdc_state sc_state;
@@ -123,6 +123,7 @@
int sc_overruns; /* number of DMA overruns */
int sc_cfg; /* current configuration */
struct fdcio sc_io;
+#define sc_handle sc_io.fdcio_handle
#define sc_reg_msr sc_io.fdcio_reg_msr
#define sc_reg_fifo sc_io.fdcio_reg_fifo
#define sc_reg_dor sc_io.fdcio_reg_dor
@@ -256,7 +257,15 @@
int fdformat __P((dev_t, struct ne7_fd_formb *, struct proc *));
void fd_do_eject __P((struct fd_softc *));
void fd_mountroot_hook __P((struct device *));
-static void fdconf __P((struct fdc_softc *));
+static int fdconf __P((struct fdc_softc *));
+static void establish_chip_type __P((
+ struct fdc_softc *,
+ bus_space_tag_t,
+ bus_type_t,
+ bus_addr_t,
+ bus_size_t,
+ bus_space_handle_t));
+
#if PIL_FDSOFT == 4
#define IE_FDSOFT IE_L4
@@ -334,6 +343,59 @@
NULL, NULL));
}
+static void
+establish_chip_type(fdc, tag, type, addr, size, handle)
+ struct fdc_softc *fdc;
+ bus_space_tag_t tag;
+ bus_type_t type;
+ bus_addr_t addr;
+ bus_size_t size;
+ bus_space_handle_t handle;
+{
+ u_int8_t v;
+
+ /*
+ * This hack from Chris Torek: apparently DOR really
+ * addresses MSR/DRS on a 82072.
+ * We used to rely on the VERSION command to tell the
+ * difference (which did not work).
+ */
+
+ /* First, check the size of the register bank */
+ if (size < 8)
+ /* It isn't a 82077 */
+ return;
+
+ /* Then probe the DOR register offset */
+ if (bus_space_probe(tag, type, addr,
+ 1, /* probe size */
+ FDREG77_DOR, /* offset */
+ 0, /* flags */
+ NULL, NULL) == 0) {
+
+ /* It isn't a 82077 */
+ return;
+ }
+
+ v = bus_space_read_1(tag, handle, FDREG77_DOR);
+ if (v == NE7_RQM) {
+ /*
+ * Value in DOR looks like it's really MSR
+ */
+ bus_space_write_1(tag, handle, FDREG77_DOR, FDC_250KBPS);
+ v = bus_space_read_1(tag, handle, FDREG77_DOR);
+ if (v == NE7_RQM) {
+ /*
+ * The value in the DOR didn't stick;
+ * it isn't a 82077
+ */
+ return;
+ }
+ }
+
+ fdc->sc_flags |= FDC_82077;
+}
+
/*
* Arguments passed between fdcattach and fdprobe.
*/
@@ -361,14 +423,14 @@
return (QUIET);
}
-static void
+static int
fdconf(fdc)
struct fdc_softc *fdc;
{
int vroom;
if (out_fdc(fdc, NE7CMD_DUMPREG) || fdcresult(fdc) != 10)
- return;
+ return (-1);
/*
* dumpreg[7] seems to be a motor-off timeout; set it to whatever
@@ -382,7 +444,27 @@
out_fdc(fdc, vroom);
out_fdc(fdc, fdc->sc_cfg);
out_fdc(fdc, 0); /* PRETRK */
- /* No result phase */
+ /* No result phase for the NE7CMD_CFG command */
+
+ if ((fdc->sc_flags & FDC_82077) != 0) {
+ /* Lock configuration across soft resets. */
+ out_fdc(fdc, NE7CMD_LOCK | CFG_LOCK);
+ if (fdcresult(fdc) != 1) {
+#ifdef DEBUG
+ printf("fdconf: CFGLOCK failed");
+#endif
+ return (-1);
+ }
+ }
+
+ return (0);
+#if 0
+ if (out_fdc(fdc, NE7CMD_VERSION) == 0 &&
+ fdcresult(fdc) == 1 && fdc->sc_status[0] == 0x90) {
+ if (fdc_debug)
+ printf("[version cmd]");
+ }
+#endif
}
/*
@@ -401,9 +483,8 @@
fdc->sc_bustag = ma->ma_bustag;
if (ma->ma_promvaddr != 0)
- fdc->sc_reg = (caddr_t)ma->ma_promvaddr;
+ fdc->sc_handle = (bus_space_handle_t)ma->ma_promvaddr;
else {
- bus_space_handle_t bh;
if (bus_space_map2(
ma->ma_bustag,
ma->ma_iospace,
@@ -411,13 +492,19 @@
ma->ma_size,
BUS_SPACE_MAP_LINEAR,
0,
- &bh) != 0) {
+ &fdc->sc_handle) != 0) {
printf("%s: cannot map registers\n", self->dv_xname);
return;
}
- fdc->sc_reg = (caddr_t)bh;
}
+ establish_chip_type(fdc,
+ ma->ma_bustag,
+ ma->ma_iospace,
+ ma->ma_paddr,
+ ma->ma_size,
+ fdc->sc_handle);
+
fdcattach(fdc, ma->ma_pri);
}
@@ -433,23 +520,27 @@
fdc->sc_bustag = sa->sa_bustag;
if (sa->sa_npromvaddrs != 0)
- fdc->sc_reg = (caddr_t)sa->sa_promvaddrs[0];
+ fdc->sc_handle = (bus_space_handle_t)sa->sa_promvaddrs[0];
else {
- bus_space_handle_t bh;
-
if (sbus_bus_map(sa->sa_bustag, sa->sa_slot,
sa->sa_offset,
sa->sa_size,
BUS_SPACE_MAP_LINEAR,
0,
- &bh) != 0) {
+ &fdc->sc_handle) != 0) {
printf("%s: cannot map control registers\n",
self->dv_xname);
return;
}
- fdc->sc_reg = (caddr_t)bh;
}
+ establish_chip_type(fdc,
+ sa->sa_bustag,
+ sa->sa_slot,
+ sa->sa_offset,
+ sa->sa_size,
+ fdc->sc_handle);
+
if (sa->sa_nintr != 0)
fdcattach(fdc, sa->sa_pri);
}
@@ -467,6 +558,30 @@
fdc->sc_flags |= FDC_EIS;
TAILQ_INIT(&fdc->sc_drives);
+ if ((fdc->sc_flags & FDC_82077) != 0) {
+ fdc->sc_reg_msr = FDREG77_MSR;
+ fdc->sc_reg_fifo = FDREG77_FIFO;
+ fdc->sc_reg_dor = FDREG77_DOR;
+ code = '7';
+ } else {
+ fdc->sc_reg_msr = FDREG72_MSR;
+ fdc->sc_reg_fifo = FDREG72_FIFO;
+ fdc->sc_reg_dor = 0;
+ code = '2';
+ }
+
+ printf(" softpri %d: chip 8207%c\n", PIL_FDSOFT, code);
+
+ /*
+ * Configure controller; enable FIFO, Implied seek, no POLL mode?.
+ * Note: CFG_EFIFO is active-low, initial threshold value: 8
+ */
+ fdc->sc_cfg = CFG_EIS|/*CFG_EFIFO|*/CFG_POLL|(8 & CFG_THRHLD_MASK);
+ if (fdconf(fdc) != 0) {
+ printf("%s: no drives attached\n", fdc->sc_dev.dv_xname);
+ return;
+ }
+
#ifdef FDC_C_HANDLER
(void)bus_intr_establish(fdc->sc_bustag, pri, 0,
fdchwintr, fdc);
@@ -480,57 +595,8 @@
BUS_INTR_ESTABLISH_SOFTINTR,
fdcswintr, fdc);
- /* Assume a 82077 */
- fdc->sc_reg_msr = &((struct fdreg_77 *)fdc->sc_reg)->fd_msr;
- fdc->sc_reg_fifo = &((struct fdreg_77 *)fdc->sc_reg)->fd_fifo;
- fdc->sc_reg_dor = &((struct fdreg_77 *)fdc->sc_reg)->fd_dor;
-
- code = '7';
- if (*fdc->sc_reg_dor == NE7_RQM) {
- /*
- * This hack from Chris Torek: apparently DOR really
- * addresses MSR/DRS on a 82072.
- * We used to rely on the VERSION command to tell the
- * difference (which did not work).
- */
- *fdc->sc_reg_dor = FDC_250KBPS;
- if (*fdc->sc_reg_dor == NE7_RQM)
- code = '2';
- }
- if (code == '7') {
- fdc->sc_flags |= FDC_82077;
- } else {
- fdc->sc_reg_msr = &((struct fdreg_72 *)fdc->sc_reg)->fd_msr;
- fdc->sc_reg_fifo = &((struct fdreg_72 *)fdc->sc_reg)->fd_fifo;
- fdc->sc_reg_dor = 0;
- }
-
-#ifdef FD_DEBUG
- if (out_fdc(fdc, NE7CMD_VERSION) == 0 &&
- fdcresult(fdc) == 1 && fdc->sc_status[0] == 0x90) {
- if (fdc_debug)
- printf("[version cmd]");
- }
-#endif
-
- /*
- * Configure controller; enable FIFO, Implied seek, no POLL mode?.
- * Note: CFG_EFIFO is active-low, initial threshold value: 8
- */
- fdc->sc_cfg = CFG_EIS|/*CFG_EFIFO|*/CFG_POLL|(8 & CFG_THRHLD_MASK);
- fdconf(fdc);
-
- if (fdc->sc_flags & FDC_82077) {
- /* Lock configuration across soft resets. */
- out_fdc(fdc, NE7CMD_LOCK | CFG_LOCK);
- if (fdcresult(fdc) != 1)
- printf(" CFGLOCK: unexpected response");
- }
-
evcnt_attach(&fdc->sc_dev, "intr", &fdc->sc_intrcnt);
- printf(" softpri %d: chip 8207%c\n", PIL_FDSOFT, code);
Home |
Main Index |
Thread Index |
Old Index