[src/trunk]: src/sys/dev/pci Add CB_BCR_RESET_ENABLE in bridge control resist...

[haya <haya%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/a2033ebe16c3
branches:  trunk
changeset: 487400:a2033ebe16c3
user:      haya <haya%NetBSD.org@localhost>
date:      Wed Jun 07 09:02:46 2000 +0000

description:
Add CB_BCR_RESET_ENABLE in bridge control resister's bit definition.

diffstat:

 sys/dev/pci/pccbb.c    |  8 +++++---
 sys/dev/pci/pccbbreg.h |  3 ++-
 2 files changed, 7 insertions(+), 4 deletions(-)

diffs (43 lines):

diff -r da3b3aabb6db -r a2033ebe16c3 sys/dev/pci/pccbb.c
--- a/sys/dev/pci/pccbb.c       Wed Jun 07 06:27:43 2000 +0000
+++ b/sys/dev/pci/pccbb.c       Wed Jun 07 09:02:46 2000 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pccbb.c,v 1.39 2000/05/08 07:31:20 kleink Exp $        */
+/*     $NetBSD: pccbb.c,v 1.40 2000/06/07 09:02:46 haya Exp $  */
 
 /*
  * Copyright (c) 1998, 1999 and 2000
@@ -1329,12 +1329,14 @@
            (sc->sc_chipset == CB_RX5C47X ? 400 * 1000 : 40 * 1000);
        u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR);
 
-       bcr |= (0x40 << 16);           /* Reset bit Assert (bit 6 at 0x3E) */
+       /* Reset bit Assert (bit 6 at 0x3E) */
+       bcr |= CB_BCR_RESET_ENABLE;
        pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr);
        delay(reset_duration);
 
        if (CBB_CARDEXIST & sc->sc_flags) {     /* A card exists.  Reset it! */
-               bcr &= ~(0x40 << 16);  /* Reset bit Deassert (bit 6 at 0x3E) */
+               /* Reset bit Deassert (bit 6 at 0x3E) */
+               bcr &= ~CB_BCR_RESET_ENABLE;
                pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr);
                delay(reset_duration);
        }
diff -r da3b3aabb6db -r a2033ebe16c3 sys/dev/pci/pccbbreg.h
--- a/sys/dev/pci/pccbbreg.h    Wed Jun 07 06:27:43 2000 +0000
+++ b/sys/dev/pci/pccbbreg.h    Wed Jun 07 09:02:46 2000 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pccbbreg.h,v 1.4 2000/01/13 08:46:46 joda Exp $        */
+/*     $NetBSD: pccbbreg.h,v 1.5 2000/06/07 09:02:47 haya Exp $        */
 /*
  * Copyright (c) 1999 HAYAKAWA Koichi.  All rights reserved.
  *
@@ -75,6 +75,7 @@
 
 
 /* PCI_BCR_INTR bits for generic PCI-CardBus bridge */
+#define CB_BCR_RESET_ENABLE     0x00400000
 #define CB_BCR_INTR_IREQ_ENABLE 0x00800000
 #define CB_BCR_PREFETCH_MEMWIN0 0x01000000
 #define CB_BCR_PREFETCH_MEMWIN1 0x02000000