[src/trunk]: src/sys/arch/mips/mips No need for flushing the cache after zero...

[soren <soren%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/a6b139a9a4b0
branches:  trunk
changeset: 485558:a6b139a9a4b0
user:      soren <soren%NetBSD.org@localhost>
date:      Sun Apr 30 23:30:47 2000 +0000

description:
No need for flushing the cache after zeroing a page uncached.

diffstat:

 sys/arch/mips/mips/pmap.c |  20 +++-----------------
 1 files changed, 3 insertions(+), 17 deletions(-)

diffs (48 lines):

diff -r 910d9c46e035 -r a6b139a9a4b0 sys/arch/mips/mips/pmap.c
--- a/sys/arch/mips/mips/pmap.c Sun Apr 30 23:01:24 2000 +0000
+++ b/sys/arch/mips/mips/pmap.c Sun Apr 30 23:30:47 2000 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pmap.c,v 1.95 2000/04/28 19:25:56 soren Exp $  */
+/*     $NetBSD: pmap.c,v 1.96 2000/04/30 23:30:47 soren Exp $  */
 
 /*-
  * Copyright (c) 1998 The NetBSD Foundation, Inc.
@@ -78,7 +78,7 @@
 
 #include <sys/cdefs.h>
 
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.95 2000/04/28 19:25:56 soren Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.96 2000/04/30 23:30:47 soren Exp $");
 
 /*
  *     Manages physical address maps.
@@ -1655,20 +1655,6 @@
                p[15] = 0;
                p += 16;
        } while (p != end);
-#if defined(MIPS3) && defined(MIPS3_L2CACHE_ABSENT)
-       /*
-        * If we have a virtually-indexed, physically-tagged WB cache,
-        * and no L2 cache to warn of aliased mappings, we must force a
-        * writeback of the destination out of the L1 cache.  If we don't,
-        * later reads (from virtual addresses mapped to the destination PA)
-        * might read old stale DRAM footprint, not the just-written data.
-        */
-       if (CPUISMIPS3 && !mips_L2CachePresent) {
-               /*XXX FIXME Not very sophisticated */
-               /*      MachFlushCache();*/
-               MachFlushDCache(MIPS_PHYS_TO_KSEG0(phys), NBPG);
-       }
-#endif
 }
 
 /*
@@ -1704,7 +1690,7 @@
         * XXX invalidate any cached lines of the destination PA
         *     here also?
         *
-        * It would be better to probably map the destination as a
+        * It would probably be better to map the destination as a
         * write-through no allocate to reduce cache thrash.
         */
        if (CPUISMIPS3 && !mips_L2CachePresent) {