[src/trunk]: src/sys/arch/sparc/sparc Rename MXCC control register.

[pk <pk%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/31fd79061f1f
branches:  trunk
changeset: 485532:31fd79061f1f
user:      pk <pk%NetBSD.org@localhost>
date:      Sun Apr 30 14:19:37 2000 +0000

description:
Rename MXCC control register.

diffstat:

 sys/arch/sparc/sparc/cache.c |  9 ++++-----
 1 files changed, 4 insertions(+), 5 deletions(-)

diffs (23 lines):

diff -r 46141de20732 -r 31fd79061f1f sys/arch/sparc/sparc/cache.c
--- a/sys/arch/sparc/sparc/cache.c      Sun Apr 30 14:18:52 2000 +0000
+++ b/sys/arch/sparc/sparc/cache.c      Sun Apr 30 14:19:37 2000 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cache.c,v 1.47 1999/02/27 13:11:22 pk Exp $ */
+/*     $NetBSD: cache.c,v 1.48 2000/04/30 14:19:37 pk Exp $ */
 
 /*
  * Copyright (c) 1996
@@ -163,10 +163,9 @@
 
        /* Now turn on MultiCache if it exists */
        if (cpuinfo.mxcc && CACHEINFO.ec_totalsize > 0) {
-               /* Multicache controller */
-               stda(MXCC_ENABLE_ADDR, ASI_CONTROL,
-                    ldda(MXCC_ENABLE_ADDR, ASI_CONTROL) |
-                    (u_int64_t)MXCC_ENABLE_BIT);
+               /* Set external cache enable bit in MXCC control register */
+               stda(MXCC_CTRLREG, ASI_CONTROL,
+                    ldda(MXCC_CTRLREG, ASI_CONTROL) | MXCC_CTRLREG_CE);
                cpuinfo.flags |= CPUFLG_CACHEPAGETABLES; /* Ok to cache PTEs */
                CACHEINFO.ec_enabled = 1;
        }