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[src/trunk]: src/sys/arch/arm32/footbridge Rework of kernel I/O & memory mapp...



details:   https://anonhg.NetBSD.org/src/rev/0642eb9ea60b
branches:  trunk
changeset: 480379:0642eb9ea60b
user:      mark <mark%NetBSD.org@localhost>
date:      Mon Jan 10 07:43:07 2000 +0000

description:
Rework of kernel I/O & memory mappings along with new implementation of
bus_space_map for PCI memory.
The mapping of system devices and I/O space has been shuffled to place them
at the top of memory leaving a larger contiguous chunk between the kernel
itself and the I/O mappings for the kernel VM area. This allows support
for kernel VM areas > 48MB.
The 144MB fixed mapping of early PCI memory space has been removed and a
new version of the bus_space_map() function has been implemented to map
PCI memory into the kernel VM area as required rather than using the fixed
mapping.
A mapping of the first 1MB of PCI memory is maintained for ISA memory
accesses and accesses to the VGA memory.

diffstat:

 sys/arch/arm32/footbridge/dc21285mem.h      |   23 +++++-
 sys/arch/arm32/footbridge/ebsa285_machdep.c |   12 +-
 sys/arch/arm32/footbridge/footbridge.c      |   21 +++--
 sys/arch/arm32/footbridge/footbridge_io.c   |  110 ++++++++++++++++++++++++++-
 4 files changed, 144 insertions(+), 22 deletions(-)

diffs (294 lines):

diff -r 509c070237c1 -r 0642eb9ea60b sys/arch/arm32/footbridge/dc21285mem.h
--- a/sys/arch/arm32/footbridge/dc21285mem.h    Mon Jan 10 07:22:35 2000 +0000
+++ b/sys/arch/arm32/footbridge/dc21285mem.h    Mon Jan 10 07:43:07 2000 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: dc21285mem.h,v 1.1 1998/09/06 02:20:33 mark Exp $      */
+/*     $NetBSD: dc21285mem.h,v 1.2 2000/01/10 07:43:07 mark Exp $      */
 
 /*
  * Copyright (c) 1997,1998 Mark Brinicombe.
@@ -73,7 +73,8 @@
 /*
  * Standard Virtual memory map used for the DC21285 'Footbridge'
  */
-
+#if 0
+/* These were the old addresses */
 #define DC21285_ARMCSR_VBASE           0xF4000000
 #define        DC21285_ARMCSR_VSIZE            0x00100000      /* 1MB */
 #define        DC21285_CACHE_FLUSH_VBASE       0xF4100000
@@ -82,9 +83,27 @@
 #define        DC21285_PCI_IO_VSIZE            0x00100000      /* 1MB */
 #define        DC21285_PCI_IACK_VBASE          0xF4300000
 #define        DC21285_PCI_IACK_VSIZE          0x00100000      /* 1MB */
+#define        DC21285_PCI_ISA_MEM_VBASE       0xF4400000
+#define        DC21285_PCI_ISA_MEM_VSIZE       0x00100000      /* 1MB */
 #define        DC21285_PCI_TYPE_1_CONFIG_VBASE 0xF5000000
 #define        DC21285_PCI_TYPE_1_CONFIG_VSIZE 0x01000000      /* 16MB */
 #define        DC21285_PCI_TYPE_0_CONFIG_VBASE 0xF6000000
 #define        DC21285_PCI_TYPE_0_CONFIG_VSIZE 0x01000000      /* 16MB */
 #define DC21285_PCI_MEM_VBASE          0xF7000000
 #define DC21285_PCI_MEM_VSIZE          0x09000000      /* 144MB */
+#endif
+
+#define DC21285_ARMCSR_VBASE           0xFD000000
+#define        DC21285_ARMCSR_VSIZE            0x00100000      /* 1MB */
+#define        DC21285_CACHE_FLUSH_VBASE       0xFD100000
+#define        DC21285_CACHE_FLUSH_VSIZE       0x00100000      /* 1MB */
+#define        DC21285_PCI_IO_VBASE            0xFD200000
+#define        DC21285_PCI_IO_VSIZE            0x00100000      /* 1MB */
+#define        DC21285_PCI_IACK_VBASE          0xFD300000
+#define        DC21285_PCI_IACK_VSIZE          0x00100000      /* 1MB */
+#define        DC21285_PCI_ISA_MEM_VBASE       0xFD400000
+#define        DC21285_PCI_ISA_MEM_VSIZE       0x00100000      /* 1MB */
+#define        DC21285_PCI_TYPE_1_CONFIG_VBASE 0xFE000000
+#define        DC21285_PCI_TYPE_1_CONFIG_VSIZE 0x01000000      /* 16MB */
+#define        DC21285_PCI_TYPE_0_CONFIG_VBASE 0xFF000000
+#define        DC21285_PCI_TYPE_0_CONFIG_VSIZE 0x01000000      /* 16MB */
diff -r 509c070237c1 -r 0642eb9ea60b sys/arch/arm32/footbridge/ebsa285_machdep.c
--- a/sys/arch/arm32/footbridge/ebsa285_machdep.c       Mon Jan 10 07:22:35 2000 +0000
+++ b/sys/arch/arm32/footbridge/ebsa285_machdep.c       Mon Jan 10 07:43:07 2000 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: ebsa285_machdep.c,v 1.9 1999/12/03 22:48:23 thorpej Exp $      */
+/*     $NetBSD: ebsa285_machdep.c,v 1.10 2000/01/10 07:43:07 mark Exp $        */
 
 /*
  * Copyright (c) 1997,1998 Mark Brinicombe.
@@ -214,6 +214,7 @@
 #ifndef CONMODE
 #define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */
 #endif
+
 int comcnspeed = CONSPEED;
 int comcnmode = CONMODE;
 
@@ -315,9 +316,9 @@
        /* Map 16MB of type 0 PCI config access */
        { DC21285_PCI_TYPE_0_CONFIG_VBASE,      DC21285_PCI_TYPE_0_CONFIG,
            DC21285_PCI_TYPE_0_CONFIG_VSIZE,    0 },
-       /* Map 128MB of 32 bit PCI address space for MEM accesses */
-       { DC21285_PCI_MEM_VBASE,                DC21285_PCI_MEM_BASE,
-           DC21285_PCI_MEM_VSIZE,              0 },
+       /* Map 1MB of 32 bit PCI address space for ISA MEM accesses via PCI */
+       { DC21285_PCI_ISA_MEM_VBASE,            DC21285_PCI_MEM_BASE,
+           DC21285_PCI_ISA_MEM_VSIZE,          0 },
        { 0, 0, 0, 0 }
 };
 
@@ -838,8 +839,7 @@
 
 #if NISA > 0
        /* Initialise the ISA subsystem early ... */
-
-       isa_cats_init(DC21285_PCI_IO_VBASE, DC21285_PCI_MEM_VBASE);
+       isa_cats_init(DC21285_PCI_IO_VBASE, DC21285_PCI_ISA_MEM_VBASE);
 #endif
 
        footbridge_pci_bs_tag_init();
diff -r 509c070237c1 -r 0642eb9ea60b sys/arch/arm32/footbridge/footbridge.c
--- a/sys/arch/arm32/footbridge/footbridge.c    Mon Jan 10 07:22:35 2000 +0000
+++ b/sys/arch/arm32/footbridge/footbridge.c    Mon Jan 10 07:43:07 2000 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: footbridge.c,v 1.2 1998/11/10 04:32:03 mark Exp $      */
+/*     $NetBSD: footbridge.c,v 1.3 2000/01/10 07:43:07 mark Exp $      */
 
 /*
  * Copyright (c) 1997,1998 Mark Brinicombe.
@@ -76,6 +76,9 @@
 
 /* Various bus space tags */
 extern struct bus_space footbridge_bs_tag;
+extern void footbridge_create_io_bs_tag(bus_space_tag_t t, void *cookie);
+extern void footbridge_create_mem_bs_tag(bus_space_tag_t t, void *cookie);
+struct bus_space footbridge_csr_tag;
 struct bus_space footbridge_pci_io_bs_tag;
 struct bus_space footbridge_pci_mem_bs_tag;
 extern struct arm32_pci_chipset footbridge_pci_chipset;
@@ -92,10 +95,10 @@
 footbridge_pci_bs_tag_init(void)
 {
        /* Set up the PCI bus tags */
-       footbridge_pci_io_bs_tag = footbridge_bs_tag;
-       footbridge_pci_io_bs_tag.bs_cookie = (void *)DC21285_PCI_IO_VBASE;
-       footbridge_pci_mem_bs_tag = footbridge_bs_tag;
-       footbridge_pci_mem_bs_tag.bs_cookie = (void *)DC21285_PCI_MEM_VBASE;
+       footbridge_create_io_bs_tag(&footbridge_pci_io_bs_tag,
+           (void *)DC21285_PCI_IO_VBASE);
+       footbridge_create_mem_bs_tag(&footbridge_pci_mem_bs_tag,
+           (void *)DC21285_PCI_MEM_BASE);
 }
 
 /*
@@ -188,10 +191,10 @@
            "parity", footbridge_intr, sc);
 
        /* Set up the PCI bus tags */
-       footbridge_pci_io_bs_tag = footbridge_bs_tag;
-       footbridge_pci_io_bs_tag.bs_cookie = (void *)DC21285_PCI_IO_VBASE;
-       footbridge_pci_mem_bs_tag = footbridge_bs_tag;
-       footbridge_pci_mem_bs_tag.bs_cookie = (void *)DC21285_PCI_MEM_VBASE;
+       footbridge_create_io_bs_tag(&footbridge_pci_io_bs_tag,
+           (void *)DC21285_PCI_IO_VBASE);
+       footbridge_create_mem_bs_tag(&footbridge_pci_mem_bs_tag,
+           (void *)DC21285_PCI_MEM_BASE);
 
        /* Attach the PCI bus */
        fba.fba_pba.pba_busname = "pci";
diff -r 509c070237c1 -r 0642eb9ea60b sys/arch/arm32/footbridge/footbridge_io.c
--- a/sys/arch/arm32/footbridge/footbridge_io.c Mon Jan 10 07:22:35 2000 +0000
+++ b/sys/arch/arm32/footbridge/footbridge_io.c Mon Jan 10 07:43:07 2000 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: footbridge_io.c,v 1.3 1999/02/27 11:14:27 mark Exp $   */
+/*     $NetBSD: footbridge_io.c,v 1.4 2000/01/10 07:43:07 mark Exp $   */
 
 /*
  * Copyright (c) 1997 Causality Limited
@@ -42,11 +42,16 @@
 #include <sys/systm.h>
 #include <machine/bus.h>
 #include <arm32/footbridge/dc21285mem.h>
+#include <vm/vm.h>
+#include <vm/vm_kern.h>
+#include <uvm/uvm_extern.h>
 
 /* Proto types for all the bus_space structure functions */
 
 bs_protos(footbridge);
 bs_protos(bs_notimpl);
+bs_map_proto(footbridge_mem);
+bs_unmap_proto(footbridge_mem);
 
 /* Declare the footbridge bus space tag */
 
@@ -121,6 +126,24 @@
        bs_notimpl_bs_c_8,
 };
 
+void footbridge_create_io_bs_tag(t, cookie)
+       struct bus_space *t;
+       void *cookie;
+{
+       *t = footbridge_bs_tag;
+       t->bs_cookie = cookie;
+}
+
+void footbridge_create_mem_bs_tag(t, cookie)
+       struct bus_space *t;
+       void *cookie;
+{
+       *t = footbridge_bs_tag;
+       t->bs_map = footbridge_mem_bs_map;
+       t->bs_unmap = footbridge_mem_bs_unmap;
+       t->bs_cookie = cookie;
+}
+
 /* bus space functions */
 
 int
@@ -132,18 +155,71 @@
        bus_space_handle_t *bshp;
 {
        /*
-        * Temporary implementation as all I/O is already mapped etc.
+        * The whole 64K of PCI space is always completely mapped during
+        * boot.
         *
-        * Eventually this function will do the mapping check for multiple maps
+        * Eventually this function will do the mapping check overlapping / 
+        * multiple mappings.
         */
-       if (bpa >= DC21285_PCI_MEM_VSIZE && bpa != DC21285_ARMCSR_VBASE)
-               panic("footbridge_bs_map: Address out of range (%08lx)\n", bpa);
 
        /* The cookie is the base address for the I/O area */
        *bshp = bpa + (bus_addr_t)t;
        return(0);
+}
+
+int
+footbridge_mem_bs_map(t, bpa, size, cacheable, bshp)
+       void *t;
+       bus_addr_t bpa;
+       bus_size_t size;
+       int cacheable;
+       bus_space_handle_t *bshp;
+{
+       bus_addr_t startpa, endpa;
+       vaddr_t va;
+
+       /* Round the allocation to page boundries */
+       startpa = trunc_page(bpa);
+       endpa = round_page(bpa + size);
+
+       /*
+        * Check for mappings below 1MB as we have this space already
+        * mapped. In practice it is only the VGA hole that takes
+        * advantage of this.
+        */
+       if (endpa < DC21285_PCI_ISA_MEM_VSIZE) {
+               /* Store the bus space handle */
+               *bshp = DC21285_PCI_ISA_MEM_VBASE + bpa;
+               return 0;
        }
 
+       /*
+        * Eventually this function will do the mapping check for overlapping / 
+        * multiple mappings
+        */
+
+       va = uvm_km_valloc(kernel_map, endpa - startpa);
+       if (va == 0)
+               return ENOMEM;
+
+       /* Store the bus space handle */
+       *bshp = va + (bpa & PGOFSET);
+
+       /* Now map the pages */
+       /* The cookie is the physical base address for the I/O area */
+       while (startpa < endpa) {
+               pmap_enter(kernel_pmap, va, (bus_addr_t)t + startpa,
+                   VM_PROT_READ | VM_PROT_WRITE, 0);
+               va += NBPG;
+               startpa += NBPG;
+       }
+
+/*     if (bpa >= DC21285_PCI_MEM_VSIZE && bpa != DC21285_ARMCSR_VBASE)
+               panic("footbridge_bs_map: Address out of range (%08lx)\n", bpa);
+*/
+       return(0);
+}
+
 int
 footbridge_bs_alloc(t, rstart, rend, size, alignment, boundary, cacheable,
     bpap, bshp)
@@ -169,6 +245,30 @@
         */
 }
 
+void
+footbridge_mem_bs_unmap(t, bsh, size)
+       void *t;
+       bus_space_handle_t bsh;
+       bus_size_t size;
+{
+       vaddr_t startva, endva;
+
+       /*
+        * Check for mappings below 1MB as we have this space permenantly
+        * mapped. In practice it is only the VGA hole that takes
+        * advantage of this.
+        */
+       if (bsh >= DC21285_PCI_ISA_MEM_VBASE
+           && bsh < (DC21285_PCI_ISA_MEM_VBASE + DC21285_PCI_ISA_MEM_VSIZE)) {
+               return;
+       }
+
+       startva = trunc_page(bsh);
+       endva = round_page(bsh + size);
+
+       uvm_km_free(kernel_map, startva, endva - startva);
+}
+
 void    
 footbridge_bs_free(t, bsh, size)
        void *t;



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