[src/netbsd-1-5]: src/sys/arch/sparc/dev New in netbsd-1-5: sw.c revision 1.3...

[pk <pk%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/0e674363dd12
branches:  netbsd-1-5
changeset: 488666:0e674363dd12
user:      pk <pk%NetBSD.org@localhost>
date:      Sat Jul 22 21:14:19 2000 +0000

description:
New in netbsd-1-5: sw.c revision 1.3; swreg.h revision 1.1.

Split si & sw drivers.

diffstat:

 sys/arch/sparc/dev/sw.c    |  979 +++++++++++++++++++++++++++++++++++++++++++++
 sys/arch/sparc/dev/swreg.h |  108 ++++
 2 files changed, 1087 insertions(+), 0 deletions(-)

diffs (truncated from 1095 to 300 lines):

diff -r 096427d8c706 -r 0e674363dd12 sys/arch/sparc/dev/sw.c
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/sparc/dev/sw.c   Sat Jul 22 21:14:19 2000 +0000
@@ -0,0 +1,979 @@
+/*     $NetBSD: sw.c,v 1.3.2.2 2000/07/22 21:14:19 pk Exp $    */
+
+/*-
+ * Copyright (c) 1996 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Adam Glass, David Jones, Gordon W. Ross, and Jason R. Thorpe.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *        This product includes software developed by the NetBSD
+ *        Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * This file contains only the machine-dependent parts of the
+ * Sun4 SCSI driver.  (Autoconfig stuff and DMA functions.)
+ * The machine-independent parts are in ncr5380sbc.c
+ *
+ * Supported hardware includes:
+ * Sun "SCSI Weird" on OBIO (sw: Sun 4/100-series)
+ * Sun SCSI-3 on VME (si: Sun 4/200-series, others)
+ *
+ * The VME variant has a bit to enable or disable the DMA engine,
+ * but that bit also gates the interrupt line from the NCR5380!
+ * Therefore, in order to get any interrupt from the 5380, (i.e.
+ * for reselect) one must clear the DMA engine transfer count and
+ * then enable DMA.  This has the further complication that you
+ * CAN NOT touch the NCR5380 while the DMA enable bit is set, so
+ * we have to turn DMA back off before we even look at the 5380.
+ *
+ * What wonderfully whacky hardware this is!
+ *
+ * David Jones wrote the initial version of this module for NetBSD/sun3,
+ * which included support for the VME adapter only. (no reselection).
+ *
+ * Gordon Ross added support for the Sun 3 OBIO adapter, and re-worked
+ * both the VME and OBIO code to support disconnect/reselect.
+ * (Required figuring out the hardware "features" noted above.)
+ *
+ * The autoconfiguration boilerplate came from Adam Glass.
+ *
+ * Jason R. Thorpe ported the autoconfiguration and VME portions to
+ * NetBSD/sparc, and added initial support for the 4/100 "SCSI Weird",
+ * a wacky OBIO variant of the VME SCSI-3.  Many thanks to Chuck Cranor
+ * for lots of helpful tips and suggestions.  Thanks also to Paul Kranenburg
+ * and Chris Torek for bits of insight needed along the way.  Thanks to
+ * David Gilbert and Andrew Gillham who risked filesystem life-and-limb
+ * for the sake of testing.  Andrew Gillham helped work out the bugs
+ * the 4/100 DMA code.
+ */
+
+/*
+ * NOTE: support for the 4/100 "SCSI Weird" is not complete!  DMA
+ * works, but interrupts (and, thus, reselection) don't.  I don't know
+ * why, and I don't have a machine to test this on further.
+ *
+ * DMA, DMA completion interrupts, and reselection work fine on my
+ * 4/260 with modern SCSI-II disks attached.  I've had reports of
+ * reselection failing on Sun Shoebox-type configurations where
+ * there are multiple non-SCSI devices behind Emulex or Adaptec
+ * bridges.  These devices pre-date the SCSI-I spec, and might not
+ * bahve the way the 5380 code expects.  For this reason, only
+ * DMA is enabled by default in this driver.
+ *
+ *     Jason R. Thorpe <thorpej%NetBSD.ORG@localhost>
+ *     December 8, 1995
+ */
+
+#include "opt_ddb.h"
+
+#include <sys/types.h>
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/malloc.h>
+#include <sys/errno.h>
+#include <sys/device.h>
+#include <sys/buf.h>
+
+#include <machine/bus.h>
+#include <machine/intr.h>
+#include <machine/autoconf.h>
+
+#include <dev/scsipi/scsi_all.h>
+#include <dev/scsipi/scsipi_all.h>
+#include <dev/scsipi/scsipi_debug.h>
+#include <dev/scsipi/scsiconf.h>
+
+#ifndef DDB
+#define        Debugger()
+#endif
+
+#ifndef DEBUG
+#define DEBUG XXX
+#endif
+
+#define COUNT_SW_LEFTOVERS     XXX     /* See sw DMA completion code */
+
+#include <dev/ic/ncr5380reg.h>
+#include <dev/ic/ncr5380var.h>
+
+#include <sparc/dev/swreg.h>
+
+/*
+ * Transfers smaller than this are done using PIO
+ * (on assumption they're not worth DMA overhead)
+ */
+#define        MIN_DMA_LEN 128
+
+/*
+ * Transfers lager than 65535 bytes need to be split-up.
+ * (Some of the FIFO logic has only 16 bits counters.)
+ * Make the size an integer multiple of the page size
+ * to avoid buf/cluster remap problems.  (paranoid?)
+ */
+#define        MAX_DMA_LEN 0xE000
+
+#ifdef DEBUG
+int sw_debug = 0;
+static int sw_link_flags = 0 /* | SDEV_DB2 */ ;
+#endif
+
+/*
+ * This structure is used to keep track of mapped DMA requests.
+ */
+struct sw_dma_handle {
+       int             dh_flags;
+#define        SIDH_BUSY       0x01            /* This DH is in use */
+#define        SIDH_OUT        0x02            /* DMA does data out (write) */
+       u_char          *dh_addr;       /* KVA of start of buffer */
+       int             dh_maplen;      /* Original data length */
+       long            dh_startingpa;  /* PA of buffer; for "sw" */
+       bus_dmamap_t    dh_dmamap;
+#define dh_dvma        dh_dmamap->dm_segs[0].ds_addr /* VA of buffer in DVMA space */
+};
+
+/*
+ * The first structure member has to be the ncr5380_softc
+ * so we can just cast to go back and fourth between them.
+ */
+struct sw_softc {
+       struct ncr5380_softc    ncr_sc;
+       bus_space_tag_t         sc_bustag;      /* bus tags */
+       bus_dma_tag_t           sc_dmatag;
+
+       struct sw_dma_handle *sc_dma;
+       int             sc_xlen;        /* length of current DMA segment. */
+       int             sc_options;     /* options for this instance. */
+};
+
+/*
+ * Options.  By default, DMA is enabled and DMA completion interrupts
+ * and reselect are disabled.  You may enable additional features
+ * the `flags' directive in your kernel's configuration file.
+ *
+ * Alternatively, you can patch your kernel with DDB or some other
+ * mechanism.  The sc_options member of the softc is OR'd with
+ * the value in sw_options.
+ *
+ * On the "sw", interrupts (and thus) reselection don't work, so they're
+ * disabled by default.  DMA is still a little dangerous, too.
+ *
+ * Note, there's a separate sw_options to make life easier.
+ */
+#define        SW_ENABLE_DMA   0x01    /* Use DMA (maybe polled) */
+#define        SW_DMA_INTR     0x02    /* DMA completion interrupts */
+#define        SW_DO_RESELECT  0x04    /* Allow disconnect/reselect */
+#define        SW_OPTIONS_MASK (SW_ENABLE_DMA|SW_DMA_INTR|SW_DO_RESELECT)
+#define SW_OPTIONS_BITS        "\10\3RESELECT\2DMA_INTR\1DMA"
+int sw_options = SW_ENABLE_DMA;
+
+static int     sw_match __P((struct device *, struct cfdata *, void *));
+static void    sw_attach __P((struct device *, struct device *, void *));
+static int     sw_intr __P((void *));
+static void    sw_reset_adapter __P((struct ncr5380_softc *));
+static void    sw_minphys __P((struct buf *));
+
+void   sw_dma_alloc __P((struct ncr5380_softc *));
+void   sw_dma_free __P((struct ncr5380_softc *));
+void   sw_dma_poll __P((struct ncr5380_softc *));
+
+void   sw_dma_setup __P((struct ncr5380_softc *));
+void   sw_dma_start __P((struct ncr5380_softc *));
+void   sw_dma_eop __P((struct ncr5380_softc *));
+void   sw_dma_stop __P((struct ncr5380_softc *));
+
+void   sw_intr_on __P((struct ncr5380_softc *));
+void   sw_intr_off __P((struct ncr5380_softc *));
+
+/* Shorthand bus space access */
+#define SWREG_READ(sc, index) \
+       bus_space_read_4((sc)->sc_regt, (sc)->sc_regh, index)
+#define SWREG_WRITE(sc, index, v) \
+       bus_space_write_4((sc)->sc_regt, (sc)->sc_regh, index, v)
+
+
+/* The Sun "SCSI Weird" 4/100 obio controller. */
+struct cfattach sw_ca = {
+       sizeof(struct sw_softc), sw_match, sw_attach
+};
+
+static int
+sw_match(parent, cf, aux)
+       struct device   *parent;
+       struct cfdata *cf;
+       void *aux;
+{
+       union obio_attach_args *uoba = aux;
+       struct obio4_attach_args *oba;
+
+       /* Nothing but a Sun 4/100 is going to have these devices. */
+       if (cpuinfo.cpu_type != CPUTYP_4_100)
+               return (0);
+
+       if (uoba->uoba_isobio4 == 0)
+               return (0);
+
+       /* Make sure there is something there... */
+       oba = &uoba->uoba_oba4;
+       return (bus_space_probe(oba->oba_bustag, 0, oba->oba_paddr,
+                               1,      /* probe size */
+                               1,      /* offset */
+                               0,      /* flags */
+                               NULL, NULL));
+}
+
+static void
+sw_attach(parent, self, aux)
+       struct device   *parent, *self;
+       void            *aux;
+{
+       struct sw_softc *sc = (struct sw_softc *) self;
+       struct ncr5380_softc *ncr_sc = &sc->ncr_sc;
+       union obio_attach_args *uoba = aux;
+       struct obio4_attach_args *oba = &uoba->uoba_oba4;
+       bus_space_handle_t bh;
+       char bits[64];
+       int i;
+
+       sc->sc_dmatag = oba->oba_dmatag;
+
+       /* Map the controller registers. */
+       if (obio_bus_map(oba->oba_bustag, oba->oba_paddr,
+                        0,
+                        SWREG_BANK_SZ,
+                        BUS_SPACE_MAP_LINEAR,
+                        0, &bh) != 0) {
+               printf("%s: cannot map registers\n", self->dv_xname);
+               return;
+       }
+
+       ncr_sc->sc_regt = oba->oba_bustag;
+       ncr_sc->sc_regh = bh;
+
+       sc->sc_options = sw_options;
+
+       ncr_sc->sc_dma_setup = sw_dma_setup;
+       ncr_sc->sc_dma_start = sw_dma_start;
+       ncr_sc->sc_dma_eop   = sw_dma_stop;
+       ncr_sc->sc_dma_stop  = sw_dma_stop;
+       ncr_sc->sc_intr_on   = sw_intr_on;
+       ncr_sc->sc_intr_off  = sw_intr_off;
+
+       /*
+        * Establish interrupt channel.
+        * Default interrupt priority always is 3.  At least, that's
+        * what my board seems to be at.  --thorpej
+        */
+       if (oba->oba_pri == -1)
+               oba->oba_pri = 3;
+