[src/netbsd-1-5]: src/sys/arch/sparc/fpu pull up 1.5 (approved by thorpej):

[mrg <mrg%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/9deb79bd5f39
branches:  netbsd-1-5
changeset: 488953:9deb79bd5f39
user:      mrg <mrg%NetBSD.org@localhost>
date:      Mon Aug 07 01:31:36 2000 +0000

description:
pull up 1.5 (approved by thorpej):
>Add fpu emulation instrumentation and fixup FCMP and FCMPE emulation for v9.
>And rename the 128-bit `x' routines to `q' to match v9 terminology:
>        i - 32-bit int
>        x - 64-bit int
>        s - 32-bit fp
>        d - 64-bit fp
>        q - 128-bit fp

diffstat:

 sys/arch/sparc/fpu/fpu_explode.c |  21 +++++++++++++++------
 1 files changed, 15 insertions(+), 6 deletions(-)

diffs (73 lines):

diff -r 42f0f995e6b9 -r 9deb79bd5f39 sys/arch/sparc/fpu/fpu_explode.c
--- a/sys/arch/sparc/fpu/fpu_explode.c  Mon Aug 07 01:31:11 2000 +0000
+++ b/sys/arch/sparc/fpu/fpu_explode.c  Mon Aug 07 01:31:36 2000 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: fpu_explode.c,v 1.4 2000/06/18 06:54:17 mrg Exp $ */
+/*     $NetBSD: fpu_explode.c,v 1.4.2.1 2000/08/07 01:31:36 mrg Exp $ */
 
 /*
  * Copyright (c) 1992, 1993
@@ -110,7 +110,7 @@
  * 64-bit int -> fpn.
  */
 int
-fpu_xitof(fp, i)
+fpu_xtof(fp, i)
        register struct fpn *fp;
        register u_int64_t i;
 {
@@ -132,7 +132,7 @@
 }
 #endif /* SUN4U */
 
-#define        mask(nbits) ((1 << (nbits)) - 1)
+#define        mask(nbits) ((1L << (nbits)) - 1)
 
 /*
  * All external floating formats convert to internal in the same manner,
@@ -213,7 +213,7 @@
  * 128-bit extended -> fpn.
  */
 int
-fpu_xtof(fp, i, j, k, l)
+fpu_qtof(fp, i, j, k, l)
        register struct fpn *fp;
        register u_int i, j, k, l;
 {
@@ -260,7 +260,7 @@
        switch (type) {
 #ifdef SUN4U
        case FTYPE_LNG:
-               s = fpu_xitof(fp, l);
+               s = fpu_xtof(fp, l);
                break;
 #endif /* SUN4U */
 
@@ -277,12 +277,13 @@
                break;
 
        case FTYPE_EXT:
-               s = fpu_xtof(fp, s, space[1], space[2], space[3]);
+               s = fpu_qtof(fp, s, space[1], space[2], space[3]);
                break;
 
        default:
                panic("fpu_explode");
        }
+
        if (s == FPC_QNAN && (fp->fp_mant[0] & FP_QUIETBIT) == 0) {
                /*
                 * Input is a signalling NaN.  All operations that return
@@ -296,4 +297,12 @@
                s = FPC_SNAN;
        }
        fp->fp_class = s;
+       DPRINTF(FPE_REG, ("fpu_explode: %%%c%d => ", (type == FTYPE_LNG) ? 'x' :
+               ((type == FTYPE_INT) ? 'i' : 
+                       ((type == FTYPE_SNG) ? 's' :
+                               ((type == FTYPE_DBL) ? 'd' :
+                                       ((type == FTYPE_EXT) ? 'q' : '?')))), 
+               reg));
+       DUMPFPN(FPE_REG, fp);
+       DPRINTF(FPE_REG, ("\n"));
 }