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[src/trunk]: src/sys/arch/sgimips/pci Use more constants and clean up a bit.
details: https://anonhg.NetBSD.org/src/rev/6f5857a702a6
branches: trunk
changeset: 487918:6f5857a702a6
user: soren <soren%NetBSD.org@localhost>
date: Wed Jun 14 22:32:20 2000 +0000
description:
Use more constants and clean up a bit.
diffstat:
sys/arch/sgimips/pci/macepci.c | 61 ++++++++++++------
sys/arch/sgimips/pci/macepcireg.h | 120 ++++++++++++++++++++++++++++---------
2 files changed, 131 insertions(+), 50 deletions(-)
diffs (259 lines):
diff -r e79006b129d4 -r 6f5857a702a6 sys/arch/sgimips/pci/macepci.c
--- a/sys/arch/sgimips/pci/macepci.c Wed Jun 14 22:29:03 2000 +0000
+++ b/sys/arch/sgimips/pci/macepci.c Wed Jun 14 22:32:20 2000 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: macepci.c,v 1.2 2000/06/14 16:32:22 soren Exp $ */
+/* $NetBSD: macepci.c,v 1.3 2000/06/14 22:32:20 soren Exp $ */
/*
* Copyright (c) 2000 Soren S. Jorvang
@@ -87,37 +87,50 @@
struct mace_attach_args *maa = aux;
struct pcibus_attach_args pba;
pcitag_t devtag;
+ pcireg_t slot;
+ u_int32_t control;
int rev;
- rev = bus_space_read_4(maa->maa_st, maa->maa_sh, PCI_REV_INFO_R);
+ rev = bus_space_read_4(maa->maa_st, maa->maa_sh, MACEPCI_REVISION);
printf(": rev %d\n", rev);
#if 0
- mace_intr_establish(maa->maa_intr, IPL_NONE , macepci_intr, sc);
+ mace_intr_establish(maa->maa_intr, IPL_NONE, macepci_intr, sc);
#endif
pc->pc_conf_read = macepci_conf_read;
pc->pc_conf_write = macepci_conf_write;
/*
- * Fixup O2 PCI slot.
+ * Fixup O2 PCI slot. Bad hack.
*/
devtag = pci_make_tag(0, 0, 3, 0);
-#if 1
- macepci_conf_write(0, devtag, 0x4, 0x00000007);
-#endif
-#if 1 /* 1 for canuck */
- macepci_conf_write(0, devtag, 0x10, 0x00001000);
-#endif
-#if 0 /* 1 for hut */
- macepci_conf_write(0, devtag, 0x18, 0x00000000);
-#endif
+
+ slot = macepci_conf_read(0, devtag, PCI_COMMAND_STATUS_REG);
+ slot |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE;
+ macepci_conf_write(0, devtag, PCI_COMMAND_STATUS_REG, slot);
+
+ slot = macepci_conf_read(0, devtag, PCI_MAPREG_START);
+ if (slot == 0xffffffe1)
+ macepci_conf_write(0, devtag, PCI_MAPREG_START, 0x00001000);
-#if 1
- printf("macepci0: ctrl %x\n", *(volatile u_int32_t *)0xbf080008);
- *(volatile u_int32_t *)0xbf080008 |= 0x000000ff;
- printf("macepci0: ctrl %x\n", *(volatile u_int32_t *)0xbf080008);
-#endif
+ slot = macepci_conf_read(0, devtag, PCI_MAPREG_START + (2 << 2));
+ if ((slot & 0xffff0000) == 0) {
+ slot += 0x00010000;
+ macepci_conf_write(0, devtag, PCI_MAPREG_START + (2 << 2),
+ 0x00000000);
+ }
+
+ /*
+ * Enable all MACE PCI interrupts. They will be masked by
+ * the CRIME code.
+ */
+ control = bus_space_read_4(maa->maa_st, maa->maa_sh, MACEPCI_CONTROL);
+ control |= CONTROL_INT_MASK;
+ bus_space_write_4(maa->maa_st, maa->maa_sh, MACEPCI_CONTROL, control);
+
+/* XXX */
+printf("macepci0: ctrl %x\n", *(volatile u_int32_t *)0xbf080008);
#if NPCI > 0
memset(&pba, 0, sizeof pba);
@@ -130,8 +143,10 @@
PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY;
pba.pba_pc = pc;
+#ifdef MACEPCI_IO_WAS_BUGGY
if (rev == 0)
pba.pba_flags &= ~PCI_FLAGS_IO_ENABLED; /* Buggy? */
+#endif
config_found(self, &pba, macepci_print);
#endif
@@ -150,6 +165,9 @@
else
printf(" bus %d", pba->pba_bus);
+ /* Mega XXX */
+ *(volatile u_int32_t *)0xb4000034 = 0; /* prime timer */
+
return UNCONF;
}
@@ -164,13 +182,14 @@
{
pcireg_t data;
+#if 1
/* XXX more generic pci error checking */
-#if 1
if ((*(volatile u_int32_t *)0xbf080004 & ~0x00100000) != 6)
panic("pcierr: %x %x", *(volatile u_int32_t *)0xbf080004,
*(volatile u_int32_t *)0xbf080000);
#endif
- *PCI_CFG_ADDR = 0x80000000 | tag | reg;
+
+ *PCI_CFG_ADDR = tag | reg;
data = *PCI_CFG_DATA;
*PCI_CFG_ADDR = 0;
@@ -193,7 +212,7 @@
if (tag == 0)
return;
- *PCI_CFG_ADDR = 0x80000000 | tag | reg;
+ *PCI_CFG_ADDR = tag | reg;
*PCI_CFG_DATA = data;
*PCI_CFG_ADDR = 0;
}
diff -r e79006b129d4 -r 6f5857a702a6 sys/arch/sgimips/pci/macepcireg.h
--- a/sys/arch/sgimips/pci/macepcireg.h Wed Jun 14 22:29:03 2000 +0000
+++ b/sys/arch/sgimips/pci/macepcireg.h Wed Jun 14 22:32:20 2000 +0000
@@ -1,40 +1,102 @@
-/* $NetBSD: macepcireg.h,v 1.1 2000/06/14 16:06:58 soren Exp $ */
+/* $NetBSD: macepcireg.h,v 1.2 2000/06/14 22:32:21 soren Exp $ */
/*
- * Copyright (c) 2000 Soren S. Jorvang. All rights reserved.
- *
+ * Copyright (c) 2000 Soren S. Jorvang
+ * All rights reserved.
+ *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions, and the following disclaimer.
+ * notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed for the
+ * NetBSD Project. See http://www.netbsd.org/ for
+ * information about NetBSD.
+ * 4. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#define PCI_ERROR_ADDR 0x0000
-#define PCI_ERROR_FLAGS 0x0004
-#define PCI_CONTROL 0x0008
-#define PCI_REV_INFO_R 0x000c
-#define PCI_FLUSH_W 0x000c
-#define PCI_CONFIG_ADDR 0x0cf8
-#define PCI_CONFIG_DATA 0x0cfc
-#define PCI_LOW_MEMORY 0x1a000000
-#define PCI_LOW_IO 0x18000000
-#define PCI_NATIVE_VIEW 0x40000000
-#define PCI_IO 0x80000000
-#define PCI_HI_MEMORY 0x280000000
-#define PCI_HI_IO 0x100000000
+#define MACEPCI_ERROR_ADDR 0x0000
+#define MACEPCI_ERROR_FLAGS 0x0004
+#define FLAGS_66MHZ_CAP 0x00000001
+#define FLAGS_BACKTOBACK_CAP 0x00000002
+#define FLAGS_DEVSEL_FAST 0x00000000
+#define FLAGS_DEVSEL_MEDIUM 0x00000004
+#define FLAGS_DEVSEL_SLOW 0x00000008
+#define FLAGS_DEVSEL_MASK 0x0000000c
+#define FLAGS_SIG_TARGET_ABORT 0x00000010
+#define FLAGS_ADDR_RETRY_ERROR 0x00010000
+#define FLAGS_ADDR_DATA_PARITY 0x00020000
+#define FLAGS_ADDR_TARGET_ABORT 0x00040000
+#define FLAGS_ADDR_MASTER_ABORT 0x00080000
+#define FLAGS_ADDR_CONFIG_SPACE 0x00100000
+#define FLAGS_ADDR_MEMORY_SPACE 0x00200000
+#define FLAGS_SIG_SYSTEM_ERROR 0x00400000
+#define FLAGS_READ_BUF_OVERRUN 0x00800000
+#define FLAGS_PARITY_ERROR 0x01000000
+#define FLAGS_INTERRUPT_TEST 0x02000000
+#define FLAGS_SYSTEM_ERROR 0x04000000
+#define FLAGS_ILL_HOST_TRANSACT 0x08000000
+#define FLAGS_RETRY_ERROR 0x10000000
+#define FLAGS_DATA_PARITY 0x20000000
+#define FLAGS_TARGET_ABORT 0x40000000
+#define FLAGS_MASTER_ABORT 0x80000000
+#define MACEPCI_CONTROL 0x0008
+#define CONTROL_INT0_SCSI0 0x00000001
+#define CONTROL_INT1_SCSI1 0x00000002
+#define CONTROL_INT2_SLOT0_A 0x00000004
+#define CONTROL_INT3_SLOT1_A 0x00000008
+#define CONTROL_INT4_SLOT2_A 0x00000010
+#define CONTROL_INT5_SLOTS_BCD 0x00000020
+#define CONTROL_INT6_SLOTS_CDB 0x00000040
+#define CONTROL_INT7_SLOTS_DBC 0x00000080
+#define CONTROL_INT_MASK 0x000000ff
+#define CONTROL_SERR_N_ENABLE 0x00000100
+#define CONTROL_REQ_N6_PRIORITY 0x00000200 /* Revision 1 only */
+#define CONTROL_PARITY_ERROR 0x00000400
+#define CONTROL_MRM_READAHEAD 0x00000800
+#define CONTROL_REG_N3_PRIORITY 0x00001000
+#define CONTROL_REG_N4_PRIORITY 0x00002000
+#define CONTROL_REG_N5_PRIORITY 0x00004000
+#define CONTROL_PARKING_ON_LAST 0x00008000
+#define CONTROL_INT0_INVAL_BUFS 0x00010000
+#define CONTROL_INT1_INVAL_BUFS 0x00020000
+#define CONTROL_INT2_INVAL_BUFS 0x00040000
+#define CONTROL_INT3_INVAL_BUFS 0x00080000
+#define CONTROL_INT4_INVAL_BUFS 0x00100000
+#define CONTROL_INT5_INVAL_BUFS 0x00200000
+#define CONTROL_INT6_INVAL_BUFS 0x00400000
+#define CONTROL_INT7_INVAL_BUFS 0x00800000
+#define CONTROL_OVERRUN_COND_I 0x01000000
+#define CONTROL_PARITY_ERROR_I 0x02000000
+#define CONTROL_SYSTEM_ERROR_I 0x04000000
+#define CONTROL_ILL_TRANS_I 0x08000000
+#define CONTROL_RETRY_ERROR_I 0x10000000
+#define CONTROL_DATA_PARITY_I 0x20000000
+#define CONTROL_TARGET_ABORT_I 0x40000000
+#define CONTROL_MASTER_ABORT_I 0x80000000
+#define MACEPCI_REVISION 0x000c
+#define MACEPCI_WBFLUSH 0x000c
+#define MACEPCI_CONFIG_ADDR 0x0cf8
+#define MACEPCI_CONFIG_DATA 0x0cfc
+
+#define MACEPCI_MEM_KSEG 0x1a000000
+#define MACEPCI_IO_KSEG 0x18000000
+#define MACEPCI_MEM_XKSEG 0x000000280000000
+#define MACEPCI_IO_XKSEG 0x000000100000000
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