[src/netbsd-1-5]: src/sys/dev/pci Pull up (approved by thorpej):

[bouyer <bouyer%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/731c94e15b01
branches:  netbsd-1-5
changeset: 488849:731c94e15b01
user:      bouyer <bouyer%NetBSD.org@localhost>
date:      Wed Aug 02 17:06:17 2000 +0000

description:
Pull up (approved by thorpej):
pciide_cmd_reg.h 1.7 -> 1.8
pciide.c 1.81 -> 1.82
Add supports for the PCI0646U2, Ultra/33 version of the PCI0646.

diffstat:

 sys/dev/pci/pciide.c         |  19 ++++++++++++++-----
 sys/dev/pci/pciide_cmd_reg.h |  16 ++++++++++++----
 2 files changed, 26 insertions(+), 9 deletions(-)

diffs (121 lines):

diff -r 306cb20fcfdd -r 731c94e15b01 sys/dev/pci/pciide.c
--- a/sys/dev/pci/pciide.c      Wed Aug 02 13:45:40 2000 +0000
+++ b/sys/dev/pci/pciide.c      Wed Aug 02 17:06:17 2000 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pciide.c,v 1.68.2.9 2000/07/27 16:28:48 bouyer Exp $   */
+/*     $NetBSD: pciide.c,v 1.68.2.10 2000/08/02 17:06:17 bouyer Exp $  */
 
 
 /*
@@ -2169,6 +2169,8 @@
 {       
        struct pciide_channel *cp;
        int channel;
+       int rev = PCI_REVISION(
+           pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG));
 
        /*
         * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE
@@ -2197,7 +2199,13 @@
                case PCI_PRODUCT_CMDTECH_648:
                        sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA;
                        sc->sc_wdcdev.UDMA_cap = 4;
+                       sc->sc_wdcdev.irqack = cmd646_9_irqack;
+                       break;
                case PCI_PRODUCT_CMDTECH_646:
+                       if (rev >= CMD0646U2_REV) {
+                               sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA;
+                               sc->sc_wdcdev.UDMA_cap = 2;
+                       }
                        sc->sc_wdcdev.irqack = cmd646_9_irqack;
                        break;
                default:
@@ -2223,6 +2231,7 @@
                        continue;
                cmd0643_9_setup_channel(&cp->wdc_channel);
        }
+       /* note - this also make sure we clear the irq disable and reset bits */
        pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE);
        WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n",
            pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54),
@@ -2254,7 +2263,7 @@
                tim = cmd0643_9_data_tim_pio[drvp->PIO_mode];
                if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) {
                        if (drvp->drive_flags & DRIVE_UDMA) {
-                               /* UltraDMA on a 0648 or 0649 */
+                               /* UltraDMA on a 646U2, 0648 or 0649 */
                                udma_reg = pciide_pci_read(sc->sc_pc,
                                    sc->sc_tag, CMD_UDMATIM(chp->channel));
                                if (drvp->UDMA_mode > 2 &&
@@ -2264,13 +2273,13 @@
                                        drvp->UDMA_mode = 2;
                                if (drvp->UDMA_mode > 2)
                                        udma_reg &= ~CMD_UDMATIM_UDMA33(drive);
-                               else
+                               else if (sc->sc_wdcdev.UDMA_cap > 2) 
                                        udma_reg |= CMD_UDMATIM_UDMA33(drive);
                                udma_reg |= CMD_UDMATIM_UDMA(drive);
                                udma_reg &= ~(CMD_UDMATIM_TIM_MASK <<
                                    CMD_UDMATIM_TIM_OFF(drive));
                                udma_reg |=
-                                   (cmd0648_9_tim_udma[drvp->UDMA_mode] <<
+                                   (cmd0646_9_tim_udma[drvp->UDMA_mode] <<
                                    CMD_UDMATIM_TIM_OFF(drive));
                                pciide_pci_write(sc->sc_pc, sc->sc_tag,
                                    CMD_UDMATIM(chp->channel), udma_reg);
@@ -2279,7 +2288,7 @@
                                 * use Multiword DMA.
                                 * Timings will be used for both PIO and DMA,
                                 * so adjust DMA mode if needed
-                                * if we have a 0648/9, turn off UDMA
+                                * if we have a 0646U2/8/9, turn off UDMA
                                 */
                                if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) {
                                        udma_reg = pciide_pci_read(sc->sc_pc,
diff -r 306cb20fcfdd -r 731c94e15b01 sys/dev/pci/pciide_cmd_reg.h
--- a/sys/dev/pci/pciide_cmd_reg.h      Wed Aug 02 13:45:40 2000 +0000
+++ b/sys/dev/pci/pciide_cmd_reg.h      Wed Aug 02 17:06:17 2000 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pciide_cmd_reg.h,v 1.6.4.1 2000/06/27 14:57:07 bouyer Exp $    */
+/*     $NetBSD: pciide_cmd_reg.h,v 1.6.4.2 2000/08/02 17:06:17 bouyer Exp $    */
 
 /*
  * Copyright (c) 1998 Manuel Bouyer.
@@ -37,6 +37,9 @@
  * Available from http://www.cmd.com/
  */
 
+/* revision of the 0646U2 */
+#define CMD0646U2_REV 0x05
+
 /* Configuration (RO) */
 #define CMD_CONF 0x50
 #define CMD_CONF_REV_MASK      0x03 /* 0640/3/6 only */
@@ -74,11 +77,16 @@
 
 /* DMA master read mode select */
 #define CMD_DMA_MODE 0x71
+#define CMD_DMA_MASK           0x03
 #define CMD_DMA                        0x00
 #define CMD_DMA_MULTIPLE       0x01
-#define CMD_DMA_LINE           0x10
+#define CMD_DMA_LINE           0x03
+/* the followings bits are only for 0646U/646U2/648/649 */
+#define CMD_DMA_IRQ(chan)      (0x4 << (chan))
+#define CMD_DMA_IRQ_DIS(chan)  (0x10 << (chan))
+#define CMD_DMA_RST            0x40
 
-/* the followings are only for 0648/9 */
+/* the followings are only for 0646U/646U2/648/649 */
 /* busmaster control/status register */
 #define CMD_BICSR      0x79
 #define CMD_BICSR_80(chan)     (0x01 << (chan))
@@ -88,7 +96,7 @@
 #define CMD_UDMATIM_UDMA33(drive) (0x04 << (drive))
 #define CMD_UDMATIM_TIM_MASK   0x3
 #define CMD_UDMATIM_TIM_OFF(drive) (4 + ((drive) * 2))
-static int8_t cmd0648_9_tim_udma[] = {0x03, 0x02, 0x01, 0x02, 0x01};
+static int8_t cmd0646_9_tim_udma[] = {0x03, 0x02, 0x01, 0x02, 0x01};
 
 /*
  * timings values for the 0643/6/8/9