[src/trunk]: src/sys/arch/sparc64/include Only use 32-bit addresses for all a...

[eeh <eeh%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/c605f3fce50f
branches:  trunk
changeset: 487658:c605f3fce50f
user:      eeh <eeh%NetBSD.org@localhost>
date:      Sat Jun 10 20:51:43 2000 +0000

description:
Only use 32-bit addresses for all accesses that don't bypass the MMU.
Makes SBus work again.

diffstat:

 sys/arch/sparc64/include/ctlreg.h |  103 +++++++++++++++++++++++++------------
 1 files changed, 70 insertions(+), 33 deletions(-)

diffs (211 lines):

diff -r e4abf40cf083 -r c605f3fce50f sys/arch/sparc64/include/ctlreg.h
--- a/sys/arch/sparc64/include/ctlreg.h Sat Jun 10 20:00:11 2000 +0000
+++ b/sys/arch/sparc64/include/ctlreg.h Sat Jun 10 20:51:43 2000 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: ctlreg.h,v 1.16 2000/06/08 17:43:24 eeh Exp $ */
+/*     $NetBSD: ctlreg.h,v 1.17 2000/06/10 20:51:43 eeh Exp $ */
 
 /*
  * Copyright (c) 1996-1999 Eduardo Horvath
@@ -471,10 +471,8 @@
                "r" ((unsigned long)(loc)), "r" (_loc_hi), \
                "r" (asi), "n" (ASI_DCACHE_TAG)); \
        } else { \
-               __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \
-" rdpr %%pstate,%1; wrpr %1,8,%%pstate; " \
-" or %0,%2,%0; lduba [%0]%%asi,%0; wrpr %1,0,%%pstate" : \
-               "=&r" (_lduba_v),  "=&r" (_pstate) : \
+               __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \
+" or %0,%1,%0; lduba [%0]%%asi,%0" : "=&r" (_lduba_v) : \
                "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \
        } \
        _lduba_v; \
@@ -530,10 +528,8 @@
                "r" ((unsigned long)(loc)), "r" (_loc_hi), \
                "r" (asi), "n" (ASI_DCACHE_TAG)); \
        } else { \
-               __asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1; " \
-" sllx %3,32,%0; wrpr %1,8,%%pstate; " \
-" or %0,%2,%0; lduha [%0]%%asi,%0; wrpr %1,0,%%pstate" : \
-               "=&r" (_lduha_v), "=&r" (_pstate) : \
+               __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \
+" or %0,%1,%0; lduha [%0]%%asi,%0" : "=&r" (_lduha_v) : \
                "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \
        } \
        _lduha_v; \
@@ -611,10 +607,8 @@
                "r" ((unsigned long)(loc)), "r" (_loc_hi), \
                "r" (asi), "n" (ASI_DCACHE_TAG)); \
        } else { \
-               __asm __volatile("wr %4,%%g0,%%asi; rdpr %%pstate,%1;" \
-" sllx %3,32,%0; wrpr %1,8,%%pstate;" \
-" or %0,%2,%0; lda [%0]%%asi,%0; wrpr %1,0,%%pstate" : \
-               "=&r" (_lda_v), "=&r" (_pstate) : \
+               __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \
+" or %0,%1,%0; lda [%0]%%asi,%0" : "=&r" (_lda_v) : \
                "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \
        } \
        _lda_v; \
@@ -632,10 +626,8 @@
                "r" ((unsigned long)(loc)), "r" (_loc_hi), \
                "r" (asi), "n" (ASI_DCACHE_TAG)); \
        } else { \
-               __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0;" \
-" rdpr %%pstate,%1; wrpr %1,8,%%pstate;" \
-" or %0,%2,%0; ldswa [%0]%%asi,%0; wrpr %1,0,%%pstate" : \
-               "=&r" (_lda_v), "=&r" (_pstate) : \
+               __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \
+" or %0,%1,%0; ldswa [%0]%%asi,%0" : "=&r" (_lda_v) : \
                "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \
        } \
        _lda_v; \
@@ -692,10 +684,9 @@
                 "=&r" (_lda_v), "=&r" (_pstate) : \
                "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi), "n" (ASI_DCACHE_TAG)); \
        } else { \
-               __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \
-" rdpr %%pstate,%1; or %0,%2,%0; wrpr %1,8,%%pstate; ldda [%0]%%asi,%0;" \
-" wrpr %1,0,%%pstate" : "=&r" (_lda_v), "=&r" (_pstate) : \
-               "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \
+               __asm __volatile("wr %3,%%g0,%%asi; sllx %2,32,%0; " \
+" or %0,%1,%0; ldda [%0]%%asi,%0" : "=&r" (_lda_v) : \
+                       "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \
        } \
        _lda_v; \
 })
@@ -731,8 +722,7 @@
                "r" (asi), "n" (ASI_DCACHE_TAG)); \
        } else { \
                __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \
-" or %0,%2,%0; ldxa [%0]%%asi,%0; " \
-" srlx %0,32,%1; srl %0,0,%0;" : \
+" or %0,%2,%0; ldxa [%0]%%asi,%0; srlx %0,32,%1; srl %0,0,%0;" : \
                "=&r" (_ldxa_lo), "=&r" (_ldxa_hi) : \
                "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \
        } \
@@ -775,11 +765,18 @@
 #define        ldxa(loc, asi) ({ \
        register unsigned long _ldxa_lo, _ldxa_hi, _loc_hi; \
        _loc_hi = (((u_int64_t)loc)>>32); \
-       __asm __volatile("wr %4,%%g0,%%asi; sllx %2,32,%0; rdpr %%pstate,%1;" \
+       if (PHYS_ASI(asi)) { \
+               __asm __volatile("wr %4,%%g0,%%asi; sllx %2,32,%0; rdpr %%pstate,%1;" \
 " or %0,%1,%0; wrpr %1,8,%%pstate; ldxa [%0]%%asi,%0; wrpr %1,0,%%pstate;" \
 " srlx %0,32,%1; srl %0,0,%0;" : \
            "=&r" (_ldxa_lo), "=&r" (_ldxa_hi) : \
            "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \
+       } else { \
+               __asm __volatile("wr %4,%%g0,%%asi; sllx %2,32,%0; " \
+" or %0,%1,%0; ldxa [%2]%%asi,%0; srlx %0,32,%1; srl %0,0,%0;" : \
+           "=&r" (_ldxa_lo), "=&r" (_ldxa_hi) : \
+           "r" ((long)(loc)), "r" (_loc_hi), "r" (asi)); \
+       } \
        ((((int64_t)_ldxa_hi)<<32)|_ldxa_lo); \
 })
 #endif
@@ -796,10 +793,18 @@
 #define        stba(loc, asi, value) ({ \
        register int _loc_hi, _pstate; \
        _loc_hi = (((u_int64_t)loc)>>32); \
-       __asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1;" \
+       if (PHYS_ASI(asi)) { \
+               __asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1;" \
 " or %3,%0,%0; wrpr %1,8,%%pstate; stba %2,[%0]%%asi; wrpr %1,0,%%pstate" : \
                "=&r" (_loc_hi), "=&r" (_pstate) : \
-               "r" ((int)(value)), "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \
+               "r" ((int)(value)), "r" ((unsigned long)(loc)), \
+               "r" (_loc_hi), "r" (asi)); \
+       } else { \
+               __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \
+" or %2,%0,%0; stba %1,[%0]%%asi" : "=&r" (_loc_hi) : \
+               "r" ((int)(value)), "r" ((unsigned long)(loc)), \
+               "r" (_loc_hi), "r" (asi)); \
+       } \
 })
 #endif
 
@@ -813,10 +818,18 @@
 #define        stha(loc, asi, value) ({ \
        register int _loc_hi, _pstate; \
        _loc_hi = (((u_int64_t)loc)>>32); \
-__asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1;" \
+       if (PHYS_ASI(asi)) { \
+               __asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1;" \
 " or %3,%0,%0; wrpr %1,8,%%pstate; stha %2,[%0]%%asi; wrpr %1,0,%%pstate" : \
                "=&r" (_loc_hi), "=&r" (_pstate) : \
-               "r" ((int)(value)), "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \
+               "r" ((int)(value)), "r" ((unsigned long)(loc)), \
+               "r" (_loc_hi), "r" (asi)); \
+       } else { \
+               __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \
+" or %2,%0,%0; stha %1,[%0]%%asi" : "=&r" (_loc_hi) : \
+           "r" ((int)(value)), "r" ((unsigned long)(loc)), \
+               "r" (_loc_hi), "r" (asi)); \
+       } \
 })
 #endif
 
@@ -830,10 +843,18 @@
 #define        sta(loc, asi, value) ({ \
        register int _loc_hi, _pstate; \
        _loc_hi = (((u_int64_t)loc)>>32); \
-       __asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1;" \
+       if (PHYS_ASI(asi)) { \
+               __asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1;" \
 " or %3,%0,%0; wrpr %1,8,%%pstate; sta %2,[%0]%%asi; wrpr %1,0,%%pstate" : \
                "=&r" (_loc_hi), "=&r" (_pstate) : \
-               "r" ((int)(value)), "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \
+               "r" ((int)(value)), "r" ((unsigned long)(loc)), \
+               "r" (_loc_hi), "r" (asi)); \
+       } else { \
+               __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \
+" or %2,%0,%0; sta %1,[%0]%%asi" : "=&r" (_loc_hi) : \
+               "r" ((int)(value)), "r" ((unsigned long)(loc)), \
+               "r" (_loc_hi), "r" (asi)); \
+       } \
 })
 #endif
 
@@ -847,10 +868,18 @@
 #define        stda(loc, asi, value) ({ \
        register int _loc_hi, _pstate; \
        _loc_hi = (((u_int64_t)loc)>>32); \
+       if (PHYS_ASI(asi)) { \
        __asm __volatile("wr %5,%%g0,%%asi; sllx %4,32,%0; rdpr %%pstate,%1; " \
 " or %3,%0,%0; wrpr %1,8,%%pstate; stda %2,[%0]%%asi; wrpr %1,0,%%pstate" : \
                "=&r" (_loc_hi), "=&r" (_pstate) : \
-               "r" ((long long)(value)), "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \
+               "r" ((long long)(value)), "r" ((unsigned long)(loc)), \
+               "r" (_loc_hi), "r" (asi)); \
+       } else { \
+               __asm __volatile("wr %4,%%g0,%%asi; sllx %3,32,%0; " \
+" or %2,%0,%0; stda %1,[%0]%%asi" : "=&r" (_loc_hi) : \
+               "r" ((long long)(value)), "r" ((unsigned long)(loc)), \
+               "r" (_loc_hi), "r" (asi)); \
+       } \
 })
 #endif
 
@@ -866,12 +895,20 @@
        int _stxa_lo, _stxa_hi, _loc_hi; \
        _stxa_lo = value; _stxa_hi = ((u_int64_t)value)>>32; \
        _loc_hi = (((u_int64_t)(u_long)loc)>>32); \
-       __asm __volatile("wr %7,%%g0,%%asi; sllx %4,32,%1; sllx %6,32,%0; " \
+       if (PHYS_ASI(asi)) { \
+               __asm __volatile("wr %7,%%g0,%%asi; sllx %4,32,%1; sllx %6,32,%0; " \
 " or %1,%3,%1; rdpr %%pstate,%3; or %0,%5,%0; wrpr %3,8,%%pstate; " \
 " stxa %1,[%0]%%asi; wrpr %3,0,%%pstate" : \
-           "=&r" (_loc_hi), "=&r" (_stxa_hi), "=&r" ((int)(_stxa_lo)): \
+               "=&r" (_loc_hi), "=&r" (_stxa_hi), "=&r" ((int)(_stxa_lo)): \
+               "r" ((int)(_stxa_lo)), "r" ((int)(_stxa_hi)), \
+               "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \
+       } else { \
+       __asm __volatile("wr %6,%%g0,%%asi; sllx %3,32,%1; sllx %5,32,%0; " \
+" or %1,%2,%1; or %0,%4,%0; stxa %1,[%0]%%asi" : \
+           "=&r" (_loc_hi), "=&r" (_stxa_hi) : \
            "r" ((int)(_stxa_lo)), "r" ((int)(_stxa_hi)), \
            "r" ((unsigned long)(loc)), "r" (_loc_hi), "r" (asi)); \
+       } \
 })
 #endif