[src/trunk]: src/sys/arch/mac68k Add some constants from Linux/mac68k to note...

[briggs <briggs%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/1f59ab37a099
branches:  trunk
changeset: 474096:1f59ab37a099
user:      briggs <briggs%NetBSD.org@localhost>
date:      Mon Jun 28 01:41:13 1999 +0000

description:
Add some constants from Linux/mac68k to note SCC, floppy, and SCSI registers.
Add some code, inspired by Linux/mac68k, to shutdown all DMA on the PSC
at startup and to disable and clear all interrupts except the SCC.

diffstat:

 sys/arch/mac68k/include/psc.h |  19 ++++++++++++++++++-
 sys/arch/mac68k/mac68k/psc.c  |  36 ++++++++++++++++++++++++++++++------
 2 files changed, 48 insertions(+), 7 deletions(-)

diffs (114 lines):

diff -r 035d9e8c10c0 -r 1f59ab37a099 sys/arch/mac68k/include/psc.h
--- a/sys/arch/mac68k/include/psc.h     Mon Jun 28 01:35:11 1999 +0000
+++ b/sys/arch/mac68k/include/psc.h     Mon Jun 28 01:41:13 1999 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: psc.h,v 1.3 1998/04/24 05:27:24 scottr Exp $   */
+/*     $NetBSD: psc.h,v 1.4 1999/06/28 01:41:13 briggs Exp $   */
 
 /*-
  * Copyright (c) 1997 David Huang <khym%bga.com@localhost>
@@ -71,6 +71,9 @@
  */
 
 /* PSC interrupt registers */
+#define PSC_ISR_BASE   0x100   /* ISR is BASE + 0x10 * level */
+#define PSC_IER_BASE   0x104   /* IER is BASE + 0x10 * level */
+
 #define        PSC_LEV3_ISR    0x130   /* level 3 interrupt status register */
 #define        PSC_LEV3_IER    0x134   /* level 3 interrupt enable register */
 #define          PSCINTR_ENET      0   /*   Ethernet interrupt */
@@ -88,10 +91,24 @@
 #define        PSC_LEV6_IER    0x164   /* level 6 interrupt enable register */
 
 /* PSC DMA channel control registers */
+#define        PSC_CTLBASE     0xc00
+
+#define        PSC_SCSI_CTL    0xc00   /* SCSI control/status */
 #define        PSC_ENETRD_CTL  0xc10   /* MACE receive DMA channel control/status */
 #define        PSC_ENETWR_CTL  0xc20   /* MACE transmit DMA channel control/status */
+#define        PSC_FDC_CTL     0xc30   /* Floppy disk */
+#define        PSC_SCCA_CTL    0xc40   /* SCC channel A */
+#define        PSC_SCCB_CTL    0xc50   /* SCC channel B */
+#define        PSC_SCCATX_CTL  0xc60   /* SCC channel A transmit */
 
 /* PSC DMA channels */
+#define        PSC_ADDRBASE    0x1000
+#define        PSC_LENBASE     0x1004
+#define        PSC_CMDBASE     0x1008
+
+#define        PSC_SCSI_ADDR   0x1000  /* SCSI DMA address register */
+#define        PSC_SCSI_LEN    0x1004  /* SCSI DMA buffer count */
+#define        PSC_SCSI_CMD    0x1008  /* SCSI DMA command register */
 #define        PSC_ENETRD_ADDR 0x1020  /* MACE receive DMA address register */
 #define        PSC_ENETRD_LEN  0x1024  /* MACE receive DMA buffer count */
 #define        PSC_ENETRD_CMD  0x1028  /* MACE receive DMA command register */
diff -r 035d9e8c10c0 -r 1f59ab37a099 sys/arch/mac68k/mac68k/psc.c
--- a/sys/arch/mac68k/mac68k/psc.c      Mon Jun 28 01:35:11 1999 +0000
+++ b/sys/arch/mac68k/mac68k/psc.c      Mon Jun 28 01:41:13 1999 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: psc.c,v 1.5 1998/08/12 05:42:46 scottr Exp $   */
+/*     $NetBSD: psc.c,v 1.6 1999/06/28 01:41:13 briggs Exp $   */
 
 /*-
  * Copyright (c) 1997 David Huang <khym%bga.com@localhost>
@@ -38,6 +38,7 @@
 #include <machine/cpu.h>
 #include <machine/psc.h>
 
+static void    psc_kill_dma __P((void));
 int            psc_lev3_intr __P((void *));
 static void    psc_lev3_noint __P((void *));
 int            psc_lev4_intr __P((void *));
@@ -81,24 +82,47 @@
 };
 
 /*
+ * Make excessively sure that all PSC DMA is shut down.
+ */
+void
+psc_kill_dma()
+{
+       int     i;
+
+       for (i = 0; i < 9; i++) {
+               psc_reg2(PSC_CTLBASE + (i << 4)) = 0x8800;
+               psc_reg2(PSC_CTLBASE + (i << 4)) = 0x1000;
+               psc_reg2(PSC_CMDBASE + (i << 5)) = 0x1100;
+               psc_reg2(PSC_CMDBASE + (i << 5) + PSC_SET1) = 0x1100;
+       }
+}
+
+/*
  * Setup the interrupt vectors and disable most of the PSC interrupts
  */
 void
 psc_init()
 {
+       int     s, i;
+
        /*
         * Only Quadra AVs have a PSC.
         */
        if (current_mac_model->class == MACH_CLASSAV) {
+               s = splhigh();
+               psc_kill_dma();
                intr_establish(psc_lev3_intr, NULL, 3);
                intr_establish(psc_lev4_intr, NULL, 4);
                intr_establish(psc_lev5_intr, NULL, 5);
                intr_establish(psc_lev6_intr, NULL, 6);
-               psc_reg1(PSC_LEV3_IER) = 0x01; /* disable level 3 interrupts */
-               psc_reg1(PSC_LEV4_IER) = 0x09; /* disable level 4 interrupts */
-               psc_reg1(PSC_LEV4_IER) = 0x86; /* except for SCC */
-               psc_reg1(PSC_LEV5_IER) = 0x03; /* disable level 5 interrupts */
-               psc_reg1(PSC_LEV6_IER) = 0x07; /* disable level 6 interrupts */
+               for (i = 3; i < 7; i++) {
+                       /* Clear any flags */
+                       psc_reg1(PSC_ISR_BASE + 0x10 * i) = 0x0F;
+                       /* Clear any interrupt enable */
+                       psc_reg1(PSC_IER_BASE + 0x10 * i) = 0x0F;
+               }
+               psc_reg1(PSC_LEV4_IER) = 0x86; /* enable SCC */
+               splx(s);
        }
 }