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[src/trunk]: src/sys/dev/pci fix a few KNF nits ..
details: https://anonhg.NetBSD.org/src/rev/9eee4ed396a8
branches: trunk
changeset: 473584:9eee4ed396a8
user: mrg <mrg%NetBSD.org@localhost>
date: Tue Jun 08 10:38:15 1999 +0000
description:
fix a few KNF nits ..
diffstat:
sys/dev/pci/pciide.c | 363 +++++++++++++++++++++++++-------------------------
1 files changed, 184 insertions(+), 179 deletions(-)
diffs (truncated from 479 to 300 lines):
diff -r 5e5b2ce38408 -r 9eee4ed396a8 sys/dev/pci/pciide.c
--- a/sys/dev/pci/pciide.c Tue Jun 08 10:35:36 1999 +0000
+++ b/sys/dev/pci/pciide.c Tue Jun 08 10:38:15 1999 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pciide.c,v 1.38 1999/05/27 09:45:50 bouyer Exp $ */
+/* $NetBSD: pciide.c,v 1.39 1999/06/08 10:38:15 mrg Exp $ */
/*
* Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved.
@@ -92,20 +92,21 @@
/* inlines for reading/writing 8-bit PCI registers */
static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t,
- int));
+ int));
+static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t,
+ int, u_int8_t));
+
static __inline u_int8_t
pciide_pci_read(pc, pa, reg)
pci_chipset_tag_t pc;
pcitag_t pa;
int reg;
{
- return (
- pci_conf_read(pc, pa, (reg & ~0x03)) >> ((reg & 0x03) * 8) & 0xff);
+
+ return (pci_conf_read(pc, pa, (reg & ~0x03)) >>
+ ((reg & 0x03) * 8) & 0xff);
}
-
-static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t,
- int, u_int8_t));
static __inline void
pciide_pci_write(pc, pa, reg, val)
pci_chipset_tag_t pc;
@@ -199,194 +200,193 @@
void pciide_print_modes __P((struct pciide_channel *));
struct pciide_product_desc {
- u_int32_t ide_product;
- int ide_flags;
- int ide_num_channels;
- const char *ide_name;
- /* init controller's capabilities for drives probe */
- void (*setup_cap) __P((struct pciide_softc*));
- /* init controller after drives probe */
- void (*setup_chip) __P((struct pciide_softc*));
- /* map channel if possible/necessary */
- void (*channel_map) __P((struct pci_attach_args *,
+ u_int32_t ide_product;
+ int ide_flags;
+ int ide_num_channels;
+ const char *ide_name;
+ /* init controller's capabilities for drives probe */
+ void (*setup_cap) __P((struct pciide_softc*));
+ /* init controller after drives probe */
+ void (*setup_chip) __P((struct pciide_softc*));
+ /* map channel if possible/necessary */
+ void (*channel_map) __P((struct pci_attach_args *,
struct pciide_channel *));
};
/* Flags for ide_flags */
-#define CMD_PCI064x_IOEN 0x01 /* CMD-style PCI_COMMAND_IO_ENABLE */
-#define ONE_QUEUE 0x02 /* device need serialised access */
+#define CMD_PCI064x_IOEN 0x01 /* CMD-style PCI_COMMAND_IO_ENABLE */
+#define ONE_QUEUE 0x02 /* device need serialised access */
/* Default product description for devices not known from this controller */
const struct pciide_product_desc default_product_desc = {
- 0,
- 0,
- PCIIDE_NUM_CHANNELS,
- "Generic PCI IDE controller",
- default_setup_cap,
- default_setup_chip,
- default_channel_map
+ 0,
+ 0,
+ PCIIDE_NUM_CHANNELS,
+ "Generic PCI IDE controller",
+ default_setup_cap,
+ default_setup_chip,
+ default_channel_map
};
-
const struct pciide_product_desc pciide_intel_products[] = {
- { PCI_PRODUCT_INTEL_82092AA,
- 0,
- PCIIDE_NUM_CHANNELS,
- "Intel 82092AA IDE controller",
- default_setup_cap,
- default_setup_chip,
- default_channel_map
- },
- { PCI_PRODUCT_INTEL_82371FB_IDE,
- 0,
- PCIIDE_NUM_CHANNELS,
- "Intel 82371FB IDE controller (PIIX)",
- piix_setup_cap,
- piix_setup_chip,
- piix_channel_map
- },
- { PCI_PRODUCT_INTEL_82371SB_IDE,
- 0,
- PCIIDE_NUM_CHANNELS,
- "Intel 82371SB IDE Interface (PIIX3)",
- piix_setup_cap,
- piix3_4_setup_chip,
- piix_channel_map
- },
- { PCI_PRODUCT_INTEL_82371AB_IDE,
- 0,
- PCIIDE_NUM_CHANNELS,
- "Intel 82371AB IDE controller (PIIX4)",
- piix_setup_cap,
- piix3_4_setup_chip,
- piix_channel_map
- },
- { 0,
- 0,
- 0,
- NULL,
- }
+ { PCI_PRODUCT_INTEL_82092AA,
+ 0,
+ PCIIDE_NUM_CHANNELS,
+ "Intel 82092AA IDE controller",
+ default_setup_cap,
+ default_setup_chip,
+ default_channel_map
+ },
+ { PCI_PRODUCT_INTEL_82371FB_IDE,
+ 0,
+ PCIIDE_NUM_CHANNELS,
+ "Intel 82371FB IDE controller (PIIX)",
+ piix_setup_cap,
+ piix_setup_chip,
+ piix_channel_map
+ },
+ { PCI_PRODUCT_INTEL_82371SB_IDE,
+ 0,
+ PCIIDE_NUM_CHANNELS,
+ "Intel 82371SB IDE Interface (PIIX3)",
+ piix_setup_cap,
+ piix3_4_setup_chip,
+ piix_channel_map
+ },
+ { PCI_PRODUCT_INTEL_82371AB_IDE,
+ 0,
+ PCIIDE_NUM_CHANNELS,
+ "Intel 82371AB IDE controller (PIIX4)",
+ piix_setup_cap,
+ piix3_4_setup_chip,
+ piix_channel_map
+ },
+ { 0,
+ 0,
+ 0,
+ NULL,
+ }
};
+
const struct pciide_product_desc pciide_cmd_products[] = {
- { PCI_PRODUCT_CMDTECH_640,
- ONE_QUEUE | CMD_PCI064x_IOEN,
- PCIIDE_NUM_CHANNELS,
- "CMD Technology PCI0640",
- default_setup_cap,
- default_setup_chip,
- cmd_channel_map
- },
- { PCI_PRODUCT_CMDTECH_643,
- ONE_QUEUE | CMD_PCI064x_IOEN,
- PCIIDE_NUM_CHANNELS,
- "CMD Technology PCI0643",
- cmd0643_6_setup_cap,
- cmd0643_6_setup_chip,
- cmd_channel_map
- },
- { PCI_PRODUCT_CMDTECH_646,
- ONE_QUEUE | CMD_PCI064x_IOEN,
- PCIIDE_NUM_CHANNELS,
- "CMD Technology PCI0646",
- cmd0643_6_setup_cap,
- cmd0643_6_setup_chip,
- cmd_channel_map
- },
- { 0,
- 0,
- 0,
- NULL,
- }
+ { PCI_PRODUCT_CMDTECH_640,
+ ONE_QUEUE | CMD_PCI064x_IOEN,
+ PCIIDE_NUM_CHANNELS,
+ "CMD Technology PCI0640",
+ default_setup_cap,
+ default_setup_chip,
+ cmd_channel_map
+ },
+ { PCI_PRODUCT_CMDTECH_643,
+ ONE_QUEUE | CMD_PCI064x_IOEN,
+ PCIIDE_NUM_CHANNELS,
+ "CMD Technology PCI0643",
+ cmd0643_6_setup_cap,
+ cmd0643_6_setup_chip,
+ cmd_channel_map
+ },
+ { PCI_PRODUCT_CMDTECH_646,
+ ONE_QUEUE | CMD_PCI064x_IOEN,
+ PCIIDE_NUM_CHANNELS,
+ "CMD Technology PCI0646",
+ cmd0643_6_setup_cap,
+ cmd0643_6_setup_chip,
+ cmd_channel_map
+ },
+ { 0,
+ 0,
+ 0,
+ NULL,
+ }
};
const struct pciide_product_desc pciide_via_products[] = {
- { PCI_PRODUCT_VIATECH_VT82C586_IDE,
- 0,
- PCIIDE_NUM_CHANNELS,
- "VIA Technologies VT82C586 (Apollo VP) IDE Controller",
- apollo_setup_cap,
- apollo_setup_chip,
- apollo_channel_map
- },
- { PCI_PRODUCT_VIATECH_VT82C586A_IDE,
- 0,
- PCIIDE_NUM_CHANNELS,
- "VIA Technologies VT82C586A IDE Controller",
- apollo_setup_cap,
- apollo_setup_chip,
- apollo_channel_map
- },
- { 0,
- 0,
- 0,
- NULL,
- }
+ { PCI_PRODUCT_VIATECH_VT82C586_IDE,
+ 0,
+ PCIIDE_NUM_CHANNELS,
+ "VIA Technologies VT82C586 (Apollo VP) IDE Controller",
+ apollo_setup_cap,
+ apollo_setup_chip,
+ apollo_channel_map
+ },
+ { PCI_PRODUCT_VIATECH_VT82C586A_IDE,
+ 0,
+ PCIIDE_NUM_CHANNELS,
+ "VIA Technologies VT82C586A IDE Controller",
+ apollo_setup_cap,
+ apollo_setup_chip,
+ apollo_channel_map
+ },
+ { 0,
+ 0,
+ 0,
+ NULL,
+ }
};
const struct pciide_product_desc pciide_cypress_products[] = {
- { PCI_PRODUCT_CONTAQ_82C693,
- 0,
- 1,
- "Contaq Microsystems CY82C693 IDE Controller",
- cy693_setup_cap,
- cy693_setup_chip,
- cy693_channel_map
- },
- { 0,
- 0,
- 0,
- NULL,
- }
+ { PCI_PRODUCT_CONTAQ_82C693,
+ 0,
+ 1,
+ "Contaq Microsystems CY82C693 IDE Controller",
+ cy693_setup_cap,
+ cy693_setup_chip,
+ cy693_channel_map
+ },
+ { 0,
+ 0,
+ 0,
+ NULL,
+ }
};
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