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[src/trunk]: src/sys/arch/pmax - Rework spl(9) implementation. Use _spl*() pr...
details: https://anonhg.NetBSD.org/src/rev/ef9eb1e26d79
branches: trunk
changeset: 473214:ef9eb1e26d79
user: nisimura <nisimura%NetBSD.org@localhost>
date: Tue May 25 04:17:57 1999 +0000
description:
- Rework spl(9) implementation. Use _spl*() processor mask manipulating
routines now reside in locore.S. No functional difference is expected.
- Replace abused splx() abuse with _splset() to change MIPS processor
interrupt mask bit. 'mips/trap.c' side will be fixed soon.
diffstat:
sys/arch/pmax/include/intr.h | 62 +++++--
sys/arch/pmax/pmax/dec_3100.c | 24 +-
sys/arch/pmax/pmax/dec_3max.c | 40 ++--
sys/arch/pmax/pmax/dec_3maxplus.c | 69 ++++----
sys/arch/pmax/pmax/dec_3min.c | 39 ++--
sys/arch/pmax/pmax/dec_5100.c | 38 ++--
sys/arch/pmax/pmax/dec_maxine.c | 48 ++---
sys/arch/pmax/pmax/locore_machdep.S | 282 +-----------------------------------
sys/arch/pmax/pmax/machdep.c | 20 +--
9 files changed, 172 insertions(+), 450 deletions(-)
diffs (truncated from 1046 to 300 lines):
diff -r 8b3b4e495026 -r ef9eb1e26d79 sys/arch/pmax/include/intr.h
--- a/sys/arch/pmax/include/intr.h Tue May 25 01:34:13 1999 +0000
+++ b/sys/arch/pmax/include/intr.h Tue May 25 04:17:57 1999 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: intr.h,v 1.5 1998/08/25 01:55:40 nisimura Exp $ */
+/* $NetBSD: intr.h,v 1.6 1999/05/25 04:17:58 nisimura Exp $ */
/*
* Copyright (c) 1998 Jonathan Stone. All rights reserved.
@@ -46,27 +46,53 @@
#ifdef _KERNEL
#ifndef _LOCORE
-typedef int spl_t;
-extern spl_t splx __P((spl_t));
-extern spl_t splsoftnet __P((void)), splsoftclock __P((void));
-extern spl_t splhigh __P((void));
-extern spl_t spl0 __P((void)); /* XXX should not enable TC on 3min */
+#include <mips/cpuregs.h>
-extern void setsoftnet __P((void)), clearsoftnet __P((void));
-extern void setsoftclock __P((void)), clearsoftclock __P((void));
+extern int _splraise __P((int));
+extern int _spllower __P((int));
+extern int _splset __P((int));
+extern int _splget __P((void));
+extern void _setsoftintr __P((int));
+extern void _clrsoftintr __P((int));
+#define setsoftclock() _setsoftintr(MIPS_SOFT_INT_MASK_0)
+#define setsoftnet() _setsoftintr(MIPS_SOFT_INT_MASK_1)
+#define clearsoftclock() _clrsoftintr(MIPS_SOFT_INT_MASK_0)
+#define clearsoftnet() _clrsoftintr(MIPS_SOFT_INT_MASK_1)
-extern int (*Mach_splnet) __P((void)), (*Mach_splbio) __P((void)),
- (*Mach_splimp) __P((void)), (*Mach_spltty) __P((void)),
- (*Mach_splclock) __P((void)), (*Mach_splstatclock) __P((void)),
- (*Mach_splnone) __P((void));
+#define splhigh() _splraise(MIPS_INT_MASK)
+#define spl0() (void)_spllower(0)
+#define splx(s) (void)_splset(s)
+#define splbio() (_splraise(splvec.splbio))
+#define splnet() (_splraise(splvec.splnet))
+#define spltty() (_splraise(splvec.spltty))
+#define splimp() (_splraise(splvec.splimp))
+#define splpmap() (_splraise(splvec.splimp))
+#define splclock() (_splraise(splvec.splclock))
+#define splstatclock() (_splraise(splvec.splstatclock))
+#define splsoftclock() _spllower(MIPS_SOFT_INT_MASK_0)
+#define splsoftnet() _splraise(MIPS_SOFT_INT_MASK_1)
-#define splnet() (*Mach_splnet)()
-#define splbio() (*Mach_splbio)()
-#define splimp() (*Mach_splimp)()
-#define spltty() (*Mach_spltty)()
-#define splclock() (*Mach_splclock)()
-#define splstatclock() (*Mach_splstatclock)()
+struct splvec {
+ int splbio;
+ int splnet;
+ int spltty;
+ int splimp;
+ int splclock;
+ int splstatclock;
+};
+extern struct splvec splvec;
+
+/* Conventionals ... */
+
+#define MIPS_SPLHIGH (MIPS_INT_MASK)
+#define MIPS_SPL0 (MIPS_INT_MASK_0|MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1)
+#define MIPS_SPL1 (MIPS_INT_MASK_1|MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1)
+#define MIPS_SPL3 (MIPS_INT_MASK_3|MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1)
+#define MIPS_SPL_0_1 (MIPS_INT_MASK_1|MIPS_SPL0)
+#define MIPS_SPL_0_1_2 (MIPS_INT_MASK_2|MIPS_SPL_0_1)
+#define MIPS_SPL_0_1_3 (MIPS_INT_MASK_3|MIPS_SPL_0_1)
+#define MIPS_SPL_0_1_2_3 (MIPS_INT_MASK_3|MIPS_SPL_0_1_2)
/*
* Index into intrcnt[], which is defined in locore
diff -r 8b3b4e495026 -r ef9eb1e26d79 sys/arch/pmax/pmax/dec_3100.c
--- a/sys/arch/pmax/pmax/dec_3100.c Tue May 25 01:34:13 1999 +0000
+++ b/sys/arch/pmax/pmax/dec_3100.c Tue May 25 04:17:57 1999 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: dec_3100.c,v 1.10 1999/04/26 09:23:21 nisimura Exp $ */
+/* $NetBSD: dec_3100.c,v 1.11 1999/05/25 04:17:57 nisimura Exp $ */
/*
* Copyright (c) 1998 Jonathan Stone. All rights reserved.
@@ -128,8 +128,7 @@
void
dec_3100_init()
{
-
- platform.iobus = "ibus";
+ platform.iobus = "baseboard";
platform.os_init = dec_3100_os_init;
platform.bus_reset = dec_3100_bus_reset;
@@ -150,19 +149,20 @@
*/
mips_hardware_intr = dec_3100_intr;
tc_enable_interrupt = dec_3100_enable_intr; /*XXX*/
- Mach_splbio = cpu_spl0;
- Mach_splnet = cpu_spl1;
- Mach_spltty = cpu_spl2;
- Mach_splimp = splhigh; /*XXX Mach_spl1(), if not for malloc()*/
- Mach_splclock = cpu_spl3;
- Mach_splstatclock = cpu_spl3;
-
mcclock_addr = (volatile struct chiptime *)
MIPS_PHYS_TO_KSEG1(KN01_SYS_CLOCK);
- mc_cpuspeed(mcclock_addr, MIPS_INT_MASK_3);
/* no high resolution timer circuit; possibly never called */
clkread = nullclkread;
+
+ splvec.splbio = MIPS_SPL0;
+ splvec.splnet = MIPS_SPL_0_1;
+ splvec.spltty = MIPS_SPL_0_1_2;
+ splvec.splimp = MIPS_SPLHIGH; /* ??? */
+ splvec.splclock = MIPS_SPL_0_1_2_3;
+ splvec.splstatclock = MIPS_SPL_0_1_2_3;
+
+ mc_cpuspeed(mcclock_addr, MIPS_INT_MASK_3);
}
@@ -244,7 +244,7 @@
}
/* If clock interrupts were enabled, re-enable them ASAP. */
- splx(MIPS_SR_INT_IE | (statusReg & MIPS_INT_MASK_3));
+ _splset(MIPS_SR_INT_IE | (statusReg & MIPS_INT_MASK_3));
#if NSII > 0
if (mask & MIPS_INT_MASK_0) {
diff -r 8b3b4e495026 -r ef9eb1e26d79 sys/arch/pmax/pmax/dec_3max.c
--- a/sys/arch/pmax/pmax/dec_3max.c Tue May 25 01:34:13 1999 +0000
+++ b/sys/arch/pmax/pmax/dec_3max.c Tue May 25 04:17:57 1999 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: dec_3max.c,v 1.11 1999/05/21 01:09:50 nisimura Exp $ */
+/* $NetBSD: dec_3max.c,v 1.12 1999/05/25 04:17:57 nisimura Exp $ */
/*
* Copyright (c) 1998 Jonathan Stone. All rights reserved.
@@ -73,7 +73,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: dec_3max.c,v 1.11 1999/05/21 01:09:50 nisimura Exp $");
+__KERNEL_RCSID(0, "$NetBSD: dec_3max.c,v 1.12 1999/05/25 04:17:57 nisimura Exp $");
#include <sys/types.h>
#include <sys/systm.h>
@@ -123,8 +123,7 @@
void
dec_3max_init()
{
-
- platform.iobus = "tcbus";
+ platform.iobus = "tc3max";
platform.os_init = dec_3max_os_init;
platform.bus_reset = dec_3max_bus_reset;
@@ -140,10 +139,7 @@
void
dec_3max_os_init()
{
- int i;
-
- volatile int *csr_addr =
- (volatile int *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR);
+ u_int32_t csr;
/* clear any memory errors from new-config probes */
*(volatile u_int *)MIPS_PHYS_TO_KSEG1(KN02_SYS_ERRADR) = 0;
@@ -153,24 +149,26 @@
* Enable ECC memory correction, turn off LEDs, and
* disable all TURBOchannel interrupts.
*/
- i = *csr_addr;
- *csr_addr = (i & ~(KN02_CSR_WRESERVED | KN02_CSR_IOINTEN)) |
- KN02_CSR_CORRECT | 0xff;
+ csr = *(u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR);
+ csr &= ~(KN02_CSR_WRESERVED|KN02_CSR_IOINTEN|KN02_CSR_CORRECT|0xff);
+ *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR) = csr;
+
mips_hardware_intr = dec_3max_intr;
tc_enable_interrupt = dec_3max_enable_intr;
- Mach_splbio = Mach_spl0;
- Mach_splnet = Mach_spl0;
- Mach_spltty = Mach_spl0;
- Mach_splimp = Mach_spl0;
- Mach_splclock = cpu_spl1;
- Mach_splstatclock = cpu_spl1;
mcclock_addr = (volatile struct chiptime *)
MIPS_PHYS_TO_KSEG1(KN02_SYS_CLOCK);
- mc_cpuspeed(mcclock_addr, MIPS_INT_MASK_1);
-
/* no high resolution timer circuit; possibly never called */
clkread = nullclkread;
+
+ splvec.splbio = MIPS_SPL0;
+ splvec.splnet = MIPS_SPL0;
+ splvec.spltty = MIPS_SPL0;
+ splvec.splimp = MIPS_SPL0;
+ splvec.splclock = MIPS_SPL_0_1;
+ splvec.splstatclock = MIPS_SPL_0_1;
+
+ mc_cpuspeed(mcclock_addr, MIPS_INT_MASK_1);
}
/*
@@ -237,7 +235,7 @@
}
slotno = 1 << (slotno + KN02_CSR_IOINTEN_SHIFT);
- s = Mach_spl0();
+ s = splhigh();
csr = *p_csr & ~(KN02_CSR_WRESERVED | 0xFF);
if (on)
*p_csr = csr | slotno;
@@ -288,7 +286,7 @@
}
/* If clock interrups were enabled, re-enable them ASAP. */
- splx(MIPS_SR_INT_IE | (statusReg & MIPS_INT_MASK_1));
+ _splset(MIPS_SR_INT_IE | (statusReg & MIPS_INT_MASK_1));
if (mask & MIPS_INT_MASK_0) {
static int intr_map[8] = { SLOT0_INTR, SLOT1_INTR, SLOT2_INTR,
diff -r 8b3b4e495026 -r ef9eb1e26d79 sys/arch/pmax/pmax/dec_3maxplus.c
--- a/sys/arch/pmax/pmax/dec_3maxplus.c Tue May 25 01:34:13 1999 +0000
+++ b/sys/arch/pmax/pmax/dec_3maxplus.c Tue May 25 04:17:57 1999 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: dec_3maxplus.c,v 1.17 1999/05/21 01:09:49 nisimura Exp $ */
+/* $NetBSD: dec_3maxplus.c,v 1.18 1999/05/25 04:17:57 nisimura Exp $ */
/*
* Copyright (c) 1998 Jonathan Stone. All rights reserved.
@@ -73,7 +73,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: dec_3maxplus.c,v 1.17 1999/05/21 01:09:49 nisimura Exp $");
+__KERNEL_RCSID(0, "$NetBSD: dec_3maxplus.c,v 1.18 1999/05/25 04:17:57 nisimura Exp $");
#include <sys/types.h>
#include <sys/systm.h>
@@ -141,7 +141,7 @@
(volatile u_int *) MIPS_PHYS_TO_KSEG1(KN03_REG_INTR);
u_int intr;
- platform.iobus = "tcioasic";
+ platform.iobus = "tc3maxplus";
platform.os_init = dec_3maxplus_os_init;
platform.bus_reset = dec_3maxplus_bus_reset;
@@ -166,39 +166,32 @@
void
dec_3maxplus_os_init()
{
- ioasic_base = MIPS_PHYS_TO_KSEG1(KN03_SYS_ASIC);
- mips_hardware_intr = dec_3maxplus_intr;
- tc_enable_interrupt = dec_3maxplus_enable_intr;
-
/* clear any pending memory errors. */
*(volatile u_int *)MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRADR) = 0;
kn03_wbflush();
- /*
- * Reset interrupts.
- */
- Mach_splbio = Mach_spl0;
- Mach_splnet = Mach_spl0;
- Mach_spltty = Mach_spl0;
- Mach_splimp = Mach_spl0; /* XXX */
- /*
- * Clock interrupts at hw priority 1 must block bio,net,tty
- * at hw priority 0.
- */
- Mach_splclock = cpu_spl1;
- Mach_splstatclock = cpu_spl1;
+ ioasic_base = MIPS_PHYS_TO_KSEG1(KN03_SYS_ASIC);
+ mips_hardware_intr = dec_3maxplus_intr;
+ tc_enable_interrupt = dec_3maxplus_enable_intr;
mcclock_addr = (volatile struct chiptime *)
MIPS_PHYS_TO_KSEG1(KN03_SYS_CLOCK);
- mc_cpuspeed(mcclock_addr, MIPS_INT_MASK_1);
+
+ /* 3MAX+ has IOASIC free-running high resolution timer */
+ clkread = kn03_clkread;
/*
- * Initialize interrupts.
+ * 3MAX+ IOASIC interrupts come through INT 0, while
+ * clock interrupt does via INT 1. splclock and splstatclock
+ * should block IOASIC activities.
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