[src/trunk]: src/sys/arch/sparc64/dev pull struct strbuf + defines into iommu...

[mrg <mrg%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/57abcf4e9103
branches:  trunk
changeset: 473188:57abcf4e9103
user:      mrg <mrg%NetBSD.org@localhost>
date:      Mon May 24 00:25:31 1999 +0000

description:
pull struct strbuf + defines into iommureg.h.  properly merge previous commit.

diffstat:

 sys/arch/sparc64/dev/iommureg.h |  29 +++++++++++++++++++++++++----
 sys/arch/sparc64/dev/sbusreg.h  |  10 ++--------
 2 files changed, 27 insertions(+), 12 deletions(-)

diffs (108 lines):

diff -r 310b2a4d026e -r 57abcf4e9103 sys/arch/sparc64/dev/iommureg.h
--- a/sys/arch/sparc64/dev/iommureg.h   Sun May 23 23:06:24 1999 +0000
+++ b/sys/arch/sparc64/dev/iommureg.h   Mon May 24 00:25:31 1999 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: iommureg.h,v 1.1 1999/05/23 07:24:02 mrg Exp $ */
+/*     $NetBSD: iommureg.h,v 1.2 1999/05/24 00:25:31 mrg Exp $ */
 
 /*
  * Copyright (c) 1992, 1993
@@ -44,17 +44,32 @@
  *     @(#)sbusreg.h   8.1 (Berkeley) 6/11/93
  */
 
+#ifndef _SPARC64_DEV_IOMMUREG_H_
+#define _SPARC64_DEV_IOMMUREG_H_
+
 /*
  * UltraSPARC IOMMU registers, common to both the sbus and PCI
  * controllers.
  */
 
+/* iommmu registers */
 struct iommureg {
        u_int64_t       iommu_cr;       /* IOMMU control register */
        u_int64_t       iommu_tsb;      /* IOMMU TSB base register */
        u_int64_t       iommu_flush;    /* IOMMU flush register */
 };
 
+/* streaming buffer registers */
+struct iommu_strbuf {
+       u_int64_t       strbuf_ctl;     /* streaming buffer control reg */
+       u_int64_t       strbuf_pgflush; /* streaming buffer page flush */
+       u_int64_t       strbuf_flushsync;/* streaming buffer flush sync */
+};
+
+/* streaming buffer control register */
+#define STRBUF_EN      0x000000000000000001LL
+#define STRBUF_D       0x000000000000000002LL
+
 /* control register bits */
 #define IOMMUCR_TSB1K          0x000000000000000000LL  /* Nummber of entries in IOTSB */
 #define IOMMUCR_TSB2K          0x000000000000010000LL
@@ -64,6 +79,7 @@
 #define IOMMUCR_TSB32K         0x000000000000050000LL
 #define IOMMUCR_TSB64K         0x000000000000060000LL
 #define IOMMUCR_TSB128K                0x000000000000070000LL
+#define IOMMUCR_TSBMASK                0xfffffffffffff8ffffLL  /* Mask for above */
 #define IOMMUCR_8KPG           0x000000000000000000LL  /* 8K iommu page size */
 #define IOMMUCR_64KPG          0x000000000000000004LL  /* 64K iommu page size */
 #define IOMMUCR_DE             0x000000000000000002LL  /* Diag enable */
@@ -81,13 +97,16 @@
 #define IOTTE_C                0x0000000000000010LL    /* Accesses to cacheable space */
 #define IOTTE_W                0x0000000000000002LL    /* Writeable */
 
+#define IOTSB_VEND     0xffffe000
+#define IOTSB_VSTART(sz)       (u_int)(IOTSB_VEND << (PGSHIFT + (sz))) 
+
 #define MAKEIOTTE(pa,w,c,s)    (((pa)&IOTTE_PAMASK)|((w)?IOTTE_W:0)|((c)?IOTTE_C:0)|((s)?IOTTE_STREAM:0)|(IOTTE_V|IOTTE_8K))
 #if 0
 /* This version generates a pointer to a int64_t */
-#define IOTSBSLOT(va,sz)       ((((((vm_offset_t)(va))-(0xff800000<<(sz))))>>(13-3))&(~7))
+#define IOTSBSLOT(va,sz)       ((((((vaddr_t)(va))-((vaddr_t)IOTSB_VSTART(sz))))>>(PGSHIFT-3))&(~7))
 #else
 /* Here we just try to create an array index */
-#define IOTSBSLOT(va,sz)       ((((((vm_offset_t)(va))-(0xff800000<<(sz))))>>(13)))
+#define IOTSBSLOT(va,sz)       ((u_int)((((((vaddr_t)(va))-((vaddr_t)IOTSB_VSTART(sz))))>>(PGSHIFT))))
 #endif
 
 /*
@@ -96,7 +115,7 @@
 
 #define INTMAP_V       0x080000000LL   /* Interrupt valid (enabled) */
 #define INTMAP_TID     0x07c000000LL   /* UPA target ID mask */
-#define INTMAP_IGN     0x0000007c0LL   /* Interrupt group no. */
+#define INTMAP_IGN     0x0000007c0LL   /* Interrupt group no (sbus only). */
 #define INTMAP_INO     0x00000003fLL   /* Interrupt number */
 #define INTMAP_INR     (INTMAP_IGN|INTMAP_INO)
 #define INTMAP_SLOT    0x000000018LL   /* SBUS slot # */
@@ -107,3 +126,5 @@
 #define INTVEC(x)      ((x)&INTMAP_INR)
 #define INTSLOT(x)     (((x)>>3)&0x7)
 #define        INTPRI(x)       ((x)&0x7)
+
+#endif /* _SPARC64_DEV_IOMMUREG_H_ */
diff -r 310b2a4d026e -r 57abcf4e9103 sys/arch/sparc64/dev/sbusreg.h
--- a/sys/arch/sparc64/dev/sbusreg.h    Sun May 23 23:06:24 1999 +0000
+++ b/sys/arch/sparc64/dev/sbusreg.h    Mon May 24 00:25:31 1999 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: sbusreg.h,v 1.5 1999/05/23 07:24:03 mrg Exp $ */
+/*     $NetBSD: sbusreg.h,v 1.6 1999/05/24 00:25:31 mrg Exp $ */
 
 /*
  * Copyright (c) 1992, 1993
@@ -123,13 +123,7 @@
 
        u_int64_t       pad4[125];
 
-       struct strbuf {
-               u_int64_t       strbuf_ctl;             /* streaming buffer control reg */      /* 1fe.0000.2800 */
-#define STRBUF_EN              0x000000000000000001LL
-#define STRBUF_D               0x000000000000000002LL
-               u_int64_t       strbuf_pgflush;         /* streaming buffer page flush */       /* 1fe.0000.2808 */
-               u_int64_t       strbuf_flushsync;       /* streaming buffer flush sync */       /* 1fe.0000.2810 */
-       } sys_strbuf;
+       struct iommu_strbuf     sys_strbuf;                                             /* 1fe.0000.2800-2810 */
 
        u_int64_t       pad5[125];