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[src/trunk]: src/sys/arch - Move MachSetPID(1) call to pmap_bootstrap() adaja...
details: https://anonhg.NetBSD.org/src/rev/5f59f4ae9bcb
branches: trunk
changeset: 473038:5f59f4ae9bcb
user: nisimura <nisimura%NetBSD.org@localhost>
date: Tue May 18 01:36:51 1999 +0000
description:
- Move MachSetPID(1) call to pmap_bootstrap() adajacent to kernel pmap
initialization code.
- Abandon mips_init_proc0() and do the 4 lines straightly in MD mach_init().
- Restore a block of code accidentally lost in prevous commit.
- Change the term 'tlbpid' to a MIPS3 nomenclature 'asid'.
- Hide PTE size exposures by symbolic names in locore.S
diffstat:
sys/arch/mips/include/cpu.h | 3 +-
sys/arch/mips/include/pmap.h | 14 ++--
sys/arch/mips/mips/genassym.cf | 5 +-
sys/arch/mips/mips/locore.S | 10 +-
sys/arch/mips/mips/mips_machdep.c | 25 +------
sys/arch/mips/mips/pmap.c | 118 ++++++++++++++++++++++------------
sys/arch/newsmips/newsmips/machdep.c | 14 ++-
sys/arch/pmax/pmax/machdep.c | 14 ++-
8 files changed, 113 insertions(+), 90 deletions(-)
diffs (truncated from 482 to 300 lines):
diff -r 0920aab62edd -r 5f59f4ae9bcb sys/arch/mips/include/cpu.h
--- a/sys/arch/mips/include/cpu.h Tue May 18 00:22:41 1999 +0000
+++ b/sys/arch/mips/include/cpu.h Tue May 18 01:36:51 1999 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.h,v 1.29 1999/03/23 22:04:01 simonb Exp $ */
+/* $NetBSD: cpu.h,v 1.30 1999/05/18 01:36:51 nisimura Exp $ */
/*-
* Copyright (c) 1992, 1993
@@ -184,7 +184,6 @@
void dumpsys __P((void));
int savectx __P((struct user *));
void mips_init_msgbuf __P((void));
-void mips_init_proc0 __P((caddr_t));
/* locore.S */
void savefpregs __P((struct proc *));
diff -r 0920aab62edd -r 5f59f4ae9bcb sys/arch/mips/include/pmap.h
--- a/sys/arch/mips/include/pmap.h Tue May 18 00:22:41 1999 +0000
+++ b/sys/arch/mips/include/pmap.h Tue May 18 01:36:51 1999 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.h,v 1.26 1999/04/24 08:10:36 simonb Exp $ */
+/* $NetBSD: pmap.h,v 1.27 1999/05/18 01:36:51 nisimura Exp $ */
/*
* Copyright (c) 1987 Carnegie-Mellon University
@@ -85,8 +85,8 @@
int pm_count; /* pmap reference count */
simple_lock_data_t pm_lock; /* lock on pmap */
struct pmap_statistics pm_stats; /* pmap statistics */
- int pm_tlbpid; /* address space tag */
- u_int pm_tlbgen; /* TLB PID generation number */
+ unsigned pm_asid; /* TLB address space tag */
+ unsigned pm_asidgen; /* its generation number */
struct segtab *pm_segtab; /* pointers to pages of PTEs */
} *pmap_t;
@@ -98,7 +98,7 @@
typedef struct pv_entry {
struct pv_entry *pv_next; /* next pv_entry */
struct pmap *pv_pmap; /* pmap where mapping lies */
- vaddr_t pv_va; /* virtual address for mapping */
+ vaddr_t pv_va; /* virtual address for mapping */
int pv_flags; /* some flags for the mapping */
} *pv_entry_t;
@@ -109,11 +109,11 @@
#ifdef _KERNEL
-char *pmap_attributes; /* reference and modify bits */
-struct pmap kernel_pmap_store;
+extern char *pmap_attributes; /* reference and modify bits */
+extern struct pmap kernel_pmap_store;
+#define pmap_kernel() (&kernel_pmap_store)
#define pmap_wired_count(pmap) ((pmap)->pm_stats.wired_count)
-#define pmap_kernel() (&kernel_pmap_store)
#define pmap_resident_count(pmap) ((pmap)->pm_stats.resident_count)
/*
diff -r 0920aab62edd -r 5f59f4ae9bcb sys/arch/mips/mips/genassym.cf
--- a/sys/arch/mips/mips/genassym.cf Tue May 18 00:22:41 1999 +0000
+++ b/sys/arch/mips/mips/genassym.cf Tue May 18 01:36:51 1999 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: genassym.cf,v 1.11 1999/03/26 03:40:41 tsubai Exp $
+# $NetBSD: genassym.cf,v 1.12 1999/05/18 01:36:52 nisimura Exp $
#
# Copyright (c) 1997
# Jonathan Stone. All rights reserved.
@@ -61,7 +61,8 @@
define P_ADDR offsetof(struct proc, p_addr)
define P_MD_REGS offsetof(struct proc, p_md.md_regs)
-define P_MD_UPTE offsetof(struct proc, p_md.md_upte)
+define P_MD_UPTE_0 offsetof(struct proc, p_md.md_upte[0])
+define P_MD_UPTE_1 offsetof(struct proc, p_md.md_upte[1])
define U_PCB_FPREGS offsetof(struct user, u_pcb.pcb_fpregs)
define U_PCB_CONTEXT offsetof(struct user, u_pcb.pcb_context)
diff -r 0920aab62edd -r 5f59f4ae9bcb sys/arch/mips/mips/locore.S
--- a/sys/arch/mips/mips/locore.S Tue May 18 00:22:41 1999 +0000
+++ b/sys/arch/mips/mips/locore.S Tue May 18 01:36:51 1999 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.S,v 1.71 1999/05/07 01:30:26 nisimura Exp $ */
+/* $NetBSD: locore.S,v 1.72 1999/05/18 01:36:52 nisimura Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -322,16 +322,16 @@
* Switch to new context.
*/
sw zero, _C_LABEL(want_resched)
- jal _C_LABEL(pmap_alloc_tlbpid) # v0 = TLB PID
+ jal _C_LABEL(pmap_alloc_asid) # v0 = new proc's ASID
move s0, a0 # BDSLOT: save p
lw a0, P_ADDR(s0) # a0 = p_addr
- lw a1, P_MD_UPTE+0(s0) # a1 = first u. pte
- lw a2, P_MD_UPTE+4(s0) # a2 = 2nd u. pte
+ lw a1, P_MD_UPTE_0(s0) # a1 = first u. pte
+ lw a2, P_MD_UPTE_1(s0) # a2 = 2nd u. pte
lw s1, _C_LABEL(mips_locore_jumpvec) + MIPSX_CPU_SWITCH_RESUME
sw s0, _C_LABEL(curproc) # set curproc
sw a0, _C_LABEL(curpcb) # set curpcb
jal ra, s1 # CPU-specific: resume process
- move a3, v0 # BDSLOT: a3 = TLB PID
+ move a3, v0 # BDSLOT: a3 = ASID
REG_PROLOGUE
REG_L v0, U_PCB_CONTEXT+SF_REG_ST(a0)
diff -r 0920aab62edd -r 5f59f4ae9bcb sys/arch/mips/mips/mips_machdep.c
--- a/sys/arch/mips/mips/mips_machdep.c Tue May 18 00:22:41 1999 +0000
+++ b/sys/arch/mips/mips/mips_machdep.c Tue May 18 01:36:51 1999 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: mips_machdep.c,v 1.51 1999/04/25 02:56:28 simonb Exp $ */
+/* $NetBSD: mips_machdep.c,v 1.52 1999/05/18 01:36:52 nisimura Exp $ */
/*-
* Copyright (c) 1998 The NetBSD Foundation, Inc.
@@ -52,7 +52,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.51 1999/04/25 02:56:28 simonb Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.52 1999/05/18 01:36:52 nisimura Exp $");
#include "opt_bufcache.h"
#include "opt_compat_netbsd.h"
@@ -1216,24 +1216,3 @@
"in last cluster (%d used)\n",
round_page(MSGBUFSIZE), sz);
}
-
-/*
- * Initialize the U-area for proc0. Since these need to be set up
- * before we can probe for memory, we have to use stolen pages before
- * they're loaded into the VM system.
- *
- * "space" is USPACE in size, must be page aligned, and in KSEG0.
- */
-void
-mips_init_proc0(space)
- caddr_t space;
-{
- /* XXX Flush cache?? */
- memset(space, 0, USPACE);
-
- proc0.p_addr = proc0paddr = (struct user *)space;
-
- curpcb = &proc0.p_addr->u_pcb;
- MachSetPID(1); /* Also establishes context using curpcb */
- proc0.p_md.md_regs = (void *)((struct frame *)((int)curpcb+USPACE) - 1);
-}
diff -r 0920aab62edd -r 5f59f4ae9bcb sys/arch/mips/mips/pmap.c
--- a/sys/arch/mips/mips/pmap.c Tue May 18 00:22:41 1999 +0000
+++ b/sys/arch/mips/mips/pmap.c Tue May 18 01:36:51 1999 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.c,v 1.59 1999/05/17 11:12:44 nisimura Exp $ */
+/* $NetBSD: pmap.c,v 1.60 1999/05/18 01:36:51 nisimura Exp $ */
/*-
* Copyright (c) 1998 The NetBSD Foundation, Inc.
@@ -78,7 +78,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.59 1999/05/17 11:12:44 nisimura Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.60 1999/05/18 01:36:51 nisimura Exp $");
/*
* Manages physical address maps.
@@ -185,10 +185,10 @@
int pv_table_npages;
struct segtab *free_segtab; /* free list kept locally */
-u_int tlbpid_gen = 1; /* TLB PID generation count */
-int tlbpid_cnt = 2; /* next available TLB PID */
pt_entry_t *Sysmap; /* kernel pte table */
-u_int Sysmapsize; /* number of pte's in Sysmap */
+unsigned Sysmapsize; /* number of pte's in Sysmap */
+unsigned pmap_next_asid = 2; /* next available ASID */
+unsigned pmap_asid_generation = 1; /* ASID generation count */
boolean_t pmap_initialized = FALSE;
@@ -213,7 +213,7 @@
/* Forward function declarations */
int pmap_remove_pv __P((pmap_t pmap, vaddr_t va, paddr_t pa));
-int pmap_alloc_tlbpid __P((struct proc *p));
+int pmap_alloc_asid __P((struct proc *p));
void pmap_zero_page __P((paddr_t phys));
void pmap_enter_pv __P((pmap_t, vaddr_t, paddr_t, u_int *));
pt_entry_t *pmap_pte __P((pmap_t, vaddr_t));
@@ -250,9 +250,41 @@
*/
void
pmap_bootstrap()
+{
+ extern int physmem;
/*
- * Initialize `FYI' variables. Note we're relying on
+ * Figure out how many PTE's are necessary to map the kernel.
+ * The '2048' comes from PAGER_MAP_SIZE in vm_pager_init().
+ * This should be kept in sync.
+ * We also reserve space for kmem_alloc_pageable() for vm_fork().
+ */
+ Sysmapsize = (VM_KMEM_SIZE + VM_PHYS_SIZE +
+ nbuf * MAXBSIZE + 16 * NCARGS) / NBPG + 2048 +
+ (maxproc * UPAGES);
+
+#ifdef SYSVSHM
+ Sysmapsize += shminfo.shmall;
+#endif
+ Sysmap = (pt_entry_t *)
+ pmap_steal_memory(sizeof(pt_entry_t) * Sysmapsize, NULL, NULL);
+
+ /*
+ * Allocate memory for the pv_heads. (A few more of the latter
+ * are allocated than are needed.)
+ *
+ * We could do this in pmap_init when we know the actual
+ * managed page pool size, but its better to use kseg0
+ * addresses rather than kernel virtual addresses mapped
+ * through the TLB.
+ */
+ pv_table_npages = physmem;
+ pv_table = (struct pv_entry *)
+ pmap_steal_memory(sizeof(struct pv_entry) * pv_table_npages,
+ NULL, NULL);
+
+ /*
+ * Initialize `FYI' variables. Note we're relying on
* the fact that BSEARCH sorts the vm_physmem[] array
* for us.
*/
@@ -269,8 +301,10 @@
*/
simple_lock_init(&pmap_kernel()->pm_lock);
pmap_kernel()->pm_count = 1;
- pmap_kernel()->pm_tlbpid = 1;
- pmap_kernel()->pm_tlbgen = tlbpid_gen;
+ pmap_kernel()->pm_asid = 1;
+ pmap_kernel()->pm_asidgen = pmap_asid_generation;
+
+ MachSetPID(1);
#if 0 /* no need, no good, no use */
proc0paddr->u_pcb.pcb_segtab = pmap_kernel()->pm_segtab = NULL;
@@ -504,8 +538,8 @@
if (pmap->pm_segtab->seg_tab[i] != 0)
panic("pmap_pinit: pm_segtab != 0");
#endif
- pmap->pm_tlbpid = 0;
- pmap->pm_tlbgen = 0;
+ pmap->pm_asid = 0;
+ pmap->pm_asidgen = 0;
}
/*
@@ -625,8 +659,8 @@
p->p_addr->u_pcb.pcb_segtab = pmap->pm_segtab;
if (p == curproc) {
- int tlbpid = pmap_alloc_tlbpid(p);
- MachSetPID(tlbpid);
+ int asid = pmap_alloc_asid(p);
+ MachSetPID(asid);
#ifdef MIPS3
if (CPUISMIPS3) {
mips3_write_xcontext_upper((u_int32_t)pmap->pm_segtab);
@@ -747,8 +781,8 @@
/*
* Flush the TLB for the given address.
*/
- if (pmap->pm_tlbgen == tlbpid_gen) {
- MachTLBFlushAddr(sva | (pmap->pm_tlbpid <<
+ if (pmap->pm_asidgen == pmap_asid_generation) {
+ MachTLBFlushAddr(sva | (pmap->pm_asid <<
MIPS_TLB_PID_SHIFT));
#ifdef DEBUG
remove_stats.flushes++;
@@ -910,8 +944,8 @@
/*
* Update the TLB if the given address is in the cache.
*/
- if (pmap->pm_tlbgen == tlbpid_gen)
- MachTLBUpdate(sva | (pmap->pm_tlbpid <<
+ if (pmap->pm_asidgen == pmap_asid_generation)
+ MachTLBUpdate(sva | (pmap->pm_asid <<
MIPS_TLB_PID_SHIFT), entry);
}
}
@@ -1020,10 +1054,10 @@
entry = (entry & ~MIPS3_PG_CACHEMODE)
| newmode;
pte->pt_entry = entry;
- if (pv->pv_pmap->pm_tlbgen ==
- tlbpid_gen)
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