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[src/trunk]: src/sys/dev/pci Rototillage; make this actually useful. To wit:
details: https://anonhg.NetBSD.org/src/rev/2bfea28d08d7
branches: trunk
changeset: 472461:2bfea28d08d7
user: nathanw <nathanw%NetBSD.org@localhost>
date: Fri Apr 30 02:47:42 1999 +0000
description:
Rototillage; make this actually useful. To wit:
- Initialize more of the Bt463's registers, instead of leaving them
in undefined states. Notably, the window type table is set up
with 8-plane pseudocolor and 24-plane truecolor modes.
- Bus-space-ify, mostly. Could use some more cleanup, but not until
the rest of the tga stuff is converted, too.
- Do the TGA/RAMDAC communication dance more carefully.
- Explain a lot more of what's going on in comments.
diffstat:
sys/dev/pci/tga_bt463.c | 275 +++++++++++++++++++++++++++++++++++++----------
1 files changed, 212 insertions(+), 63 deletions(-)
diffs (truncated from 418 to 300 lines):
diff -r fcefd3898497 -r 2bfea28d08d7 sys/dev/pci/tga_bt463.c
--- a/sys/dev/pci/tga_bt463.c Fri Apr 30 02:12:03 1999 +0000
+++ b/sys/dev/pci/tga_bt463.c Fri Apr 30 02:47:42 1999 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tga_bt463.c,v 1.3 1999/03/24 05:51:21 mrg Exp $ */
+/* $NetBSD: tga_bt463.c,v 1.4 1999/04/30 02:47:42 nathanw Exp $ */
/*-
* Copyright (c) 1998 The NetBSD Foundation, Inc.
@@ -123,23 +123,30 @@
char cmap_r[BT463_NCMAP_ENTRIES]; /* colormap */
char cmap_g[BT463_NCMAP_ENTRIES];
char cmap_b[BT463_NCMAP_ENTRIES];
+ int window_type[16]; /* 16 24-bit window type table entries */
};
#define DATA_CURCMAP_CHANGED 0x01 /* cursor colormap changed */
#define DATA_CMAP_CHANGED 0x02 /* colormap changed */
-#define DATA_ALL_CHANGED 0x03
+#define DATA_WTYPE_CHANGED 0x04 /* window type table changed */
+#define DATA_ALL_CHANGED 0x07
/*
* Internal functions.
*/
-inline void tga_bt463_wr_d __P((volatile tga_reg_t *, u_int, u_int8_t));
-inline u_int8_t tga_bt463_rd_d __P((volatile tga_reg_t *, u_int));
-inline void tga_bt463_wraddr __P((volatile tga_reg_t *, u_int16_t));
-void tga_bt463_update __P((struct tga_devconfig *, struct bt463data *));
+inline void tga_bt463_wr_d __P((bus_space_tag_t, bus_space_handle_t,
+ u_int, u_int8_t));
+inline u_int8_t tga_bt463_rd_d __P((bus_space_tag_t, bus_space_handle_t,
+ u_int));
+inline void tga_bt463_wraddr __P((bus_space_tag_t, bus_space_handle_t,
+ u_int16_t));
-#define tga_bt463_sched_update(dc) \
- ((dc)->dc_regs[TGA_REG_SISR] = 0x00010000) /* XXX */
+void tga_bt463_update __P((bus_space_tag_t, bus_space_handle_t,
+ struct bt463data *));
+#define tga_bt463_sched_update(tag,regs) \
+ bus_space_write_4((tag), (regs), (TGA_REG_SISR*4), (0x00010000))
+
/*****************************************************************************/
/*
@@ -152,34 +159,53 @@
int alloc;
{
struct bt463data tmp, *data;
+ bus_space_tag_t tag;
+ bus_space_handle_t regs;
int i;
/*
* Init the BT463 for normal operation.
*/
+ tag = dc->dc_memt;
+ bus_space_subregion(tag, dc->dc_vaddr, TGA_MEM_CREGS, 512,
+ ®s);
/*
- * Select:
- *
- * Overlay mapping: mapped to common palette.
- * 14 window type entries.
+ * Setup:
+ * reg 0: 4:1 multiplexing, 25/75 blink.
+ * reg 1: Overlay mapping: mapped to common palette,
+ * 14 window type entries, 24-plane configuration mode,
+ * 4 overlay planes, underlays disabled, no cursor.
+ * reg 2: sync-on-green disabled, pedestal enabled.
*/
- tga_bt463_wraddr(dc->dc_regs, BT463_IREG_COMMAND_1);
- tga_bt463_wr_d(dc->dc_regs, BT463_REG_IREG_DATA, 0x48);
+ tga_bt463_wraddr(tag, regs, BT463_IREG_COMMAND_0);
+ tga_bt463_wr_d(tag, regs, BT463_REG_IREG_DATA, 0x40);
+
+ tga_bt463_wraddr(tag, regs, BT463_IREG_COMMAND_1);
+ tga_bt463_wr_d(tag, regs, BT463_REG_IREG_DATA, 0x48);
+
+ tga_bt463_wraddr(tag, regs, BT463_IREG_COMMAND_2);
+ tga_bt463_wr_d(tag, regs, BT463_REG_IREG_DATA, 0x40);
/*
* Initialize the read mask.
*/
- tga_bt463_wraddr(dc->dc_regs, BT463_IREG_READ_MASK_P0_P7);
+ tga_bt463_wraddr(tag, regs, BT463_IREG_READ_MASK_P0_P7);
for (i = 0; i < 3; i++)
- tga_bt463_wr_d(dc->dc_regs, BT463_REG_IREG_DATA, 0xff);
+ tga_bt463_wr_d(tag, regs, BT463_REG_IREG_DATA, 0xff);
/*
* Initialize the blink mask.
*/
- tga_bt463_wraddr(dc->dc_regs, BT463_IREG_BLINK_MASK_P0_P7);
+ tga_bt463_wraddr(tag, regs, BT463_IREG_BLINK_MASK_P0_P7);
for (i = 0; i < 3; i++)
- tga_bt463_wr_d(dc->dc_regs, BT463_REG_IREG_DATA, 0);
+ tga_bt463_wr_d(tag, regs, BT463_REG_IREG_DATA, 0);
+
+ /*
+ * Clear test register
+ */
+ tga_bt463_wraddr(tag, regs, BT463_IREG_TEST);
+ tga_bt463_wr_d(tag, regs, BT463_REG_IREG_DATA, 0);
/*
* If we should allocate a new private info struct, do so.
@@ -212,9 +238,55 @@
for (i = 1; i < 256; i++)
data->cmap_r[i] = data->cmap_g[i] = data->cmap_b[i] = 255;
- tga_bt463_update(dc, data);
+
+ /* Initialize the window type table:
+ * Entry 0: 8-plane pseudocolor in the bottom 8 bits,
+ * overlays disabled, colormap starting at 0.
+ *
+ * Lookup table bypass: no ( 0 << 23 & 0x800000) 0
+ * Colormap address: 0x000 (0x000 << 17 & 0x7e0000) 0
+ * Overlay mask: 0x0 ( 0 << 13 & 0x01e000) 0
+ * Overlay location: P<27:24> ( 0 << 12 & 0x001000) 0
+ * Display mode: Pseudocolor ( 1 << 9 & 0x000e00) 0x200
+ * Number of planes: 8 ( 8 << 5 & 0x0001e0) 0x100
+ * Plane shift: 16 ( 16 << 0 & 0x00001f) 10
+ * --------
+ * 0x310
+ */
+ data->window_type[0] = 0x310;
+ /* The colormap interface to the world only supports one colormap,
+ * so having an entry for the 'alternate' colormap in the bt463
+ * probably isn't useful.
+ */
+ /* Entry 1: 24-plane truecolor, overlays disabled. */
+ data->window_type[1] = 0x200;
- dc->dc_regs[TGA_REG_SISR] = 0x00000001; /* XXX */
+ /* Fill the remaining table entries with clones of entry 0 until we
+ * figure out a better use for them.
+ */
+
+ for (i = 2; i < BT463_NWTYPE_ENTRIES; i++) {
+ data->window_type[i] = 0x310;
+ }
+
+ /* The Bt463 won't accept window type table data
+ * except during a blanking interval. Normally we would
+ * do this by scheduling an interrupt, but this is run
+ * during autoconfiguration, when interrupts are disabled.
+ * So we spin on the end-of-frame interrupt bit.
+ */
+
+ bus_space_write_4(tag, regs, TGA_REG_SISR*4, 0x00010001);
+ bus_space_barrier(tag, regs, TGA_REG_SISR*4, 4, BUS_SPACE_BARRIER_WRITE);
+ while ((bus_space_read_4(tag, regs, (TGA_REG_SISR * 4))& 0x00000001) == 0);
+
+ tga_bt463_update(tag, regs, data);
+
+ bus_space_write_4(tag, regs, TGA_REG_SISR*4, 0x00000001);
+ bus_space_barrier(tag, regs, TGA_REG_SISR*4, 4, BUS_SPACE_BARRIER_WRITE);
+
+ tga_bt463_sched_update(tag, regs);
+
}
int
@@ -223,8 +295,14 @@
struct wsdisplay_cmap *cmapp;
{
struct bt463data *data = dc->dc_ramdac_private;
+ bus_space_tag_t tag = dc->dc_memt;
+ bus_space_handle_t regs;
int count, index, s;
+ bus_space_subregion(tag, dc->dc_vaddr, TGA_MEM_CREGS, 512,
+ ®s);
+
+
if ((u_int)cmapp->index >= BT463_NCMAP_ENTRIES ||
((u_int)cmapp->index + (u_int)cmapp->count) > BT463_NCMAP_ENTRIES)
return (EINVAL);
@@ -243,7 +321,7 @@
data->changed |= DATA_CMAP_CHANGED;
- tga_bt463_sched_update(dc);
+ tga_bt463_sched_update(tag, regs);
splx(s);
return (0);
@@ -300,6 +378,11 @@
{
struct bt463data *data = dc->dc_ramdac_private;
int count, index;
+ bus_space_tag_t tag = dc->dc_memt;
+ bus_space_handle_t regs;
+
+ bus_space_subregion(tag, dc->dc_vaddr, TGA_MEM_CREGS, 512,
+ ®s);
/* can't fail; parameters have already been checked. */
count = cursorp->cmap.count;
@@ -308,7 +391,7 @@
copyin(cursorp->cmap.green, &data->curcmap_g[index], count);
copyin(cursorp->cmap.blue, &data->curcmap_b[index], count);
data->changed |= DATA_CURCMAP_CHANGED;
- tga_bt463_sched_update(dc);
+ tga_bt463_sched_update(tag, regs);
}
int
@@ -344,11 +427,22 @@
void *v;
{
struct tga_devconfig *dc = v;
+ bus_space_tag_t tag = dc->dc_memt;
+ bus_space_handle_t regs;
- if ((dc->dc_regs[TGA_REG_SISR] & 0x00010001) != 0x00010001)
+ bus_space_subregion(tag, dc->dc_vaddr, TGA_MEM_CREGS, 512,
+ ®s);
+
+ if ( (bus_space_read_4(tag, regs, TGA_REG_SISR*4) & 0x00010001) !=
+ 0x00010001) {
+ printf("Spurious interrupt");
return 0;
- tga_bt463_update(dc, dc->dc_ramdac_private);
- dc->dc_regs[TGA_REG_SISR] = 0x00000001;
+ }
+
+ tga_bt463_update(tag, regs, dc->dc_ramdac_private);
+
+ bus_space_write_4(tag, regs, TGA_REG_SISR*4, 0x00000001);
+ bus_space_barrier(tag, regs, TGA_REG_SISR*4, 4, BUS_SPACE_BARRIER_WRITE);
return (1);
}
@@ -359,8 +453,9 @@
*/
inline void
-tga_bt463_wr_d(tgaregs, btreg, val)
- volatile tga_reg_t *tgaregs;
+tga_bt463_wr_d(tag, regs, btreg, val)
+ bus_space_tag_t tag;
+ bus_space_handle_t regs;
u_int btreg;
u_int8_t val;
{
@@ -368,16 +463,28 @@
if (btreg > BT463_REG_MAX)
panic("tga_bt463_wr_d: reg %d out of range\n", btreg);
- /* XXX */
- tgaregs[TGA_REG_EPDR] = (btreg << 10) | (0 << 9) || (0 << 8) | val;
-#ifdef __alpha__
- alpha_mb();
-#endif
+ /*
+ * In spite of the 21030 documentation, to set the MPU bus bits for
+ * a write, you set them in the upper bits of EPDR, not EPSR.
+ */
+
+ /*
+ * Strobe CE# (high->low->high) since status and data are latched on
+ * the falling and rising edges of this active-low signal.
+ */
+
+ bus_space_barrier(tag, regs, TGA_REG_EPDR*4, 4, BUS_SPACE_BARRIER_WRITE);
+ bus_space_write_4(tag, regs, TGA_REG_EPDR*4, (btreg << 10 ) | 0x100 | val);
+ bus_space_barrier(tag, regs, TGA_REG_EPDR*4, 4, BUS_SPACE_BARRIER_WRITE);
+ bus_space_write_4(tag, regs, TGA_REG_EPDR*4, (btreg << 10 ) | 0x000 | val);
+ bus_space_barrier(tag, regs, TGA_REG_EPDR*4, 4, BUS_SPACE_BARRIER_WRITE);
+ bus_space_write_4(tag, regs, TGA_REG_EPDR*4, (btreg << 10 ) | 0x100 | val);
}
inline u_int8_t
-tga_bt463_rd_d(tgaregs, btreg)
- volatile tga_reg_t *tgaregs;
+tga_bt463_rd_d(tag, regs, btreg)
+ bus_space_tag_t tag;
+ bus_space_handle_t regs;
u_int btreg;
{
tga_reg_t rdval;
@@ -385,58 +492,100 @@
if (btreg > BT463_REG_MAX)
panic("tga_bt463_rd_d: reg %d out of range\n", btreg);
- tgaregs[TGA_REG_EPSR] = (btreg << 2) | (0x1 << 1) | 0; /* XXX */
-#ifdef __alpha__
- alpha_mb();
-#endif
+ /*
+ * Strobe CE# (high->low->high) since status and data are latched on
+ * the falling and rising edges of this active-low signal.
+ */
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