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[src/trunk]: src/sys/arch/pmax/pmax - Sweep machdep.c; mostly imported from a...
details: https://anonhg.NetBSD.org/src/rev/a37d0a29c2d2
branches: trunk
changeset: 472268:a37d0a29c2d2
user: nisimura <nisimura%NetBSD.org@localhost>
date: Mon Apr 26 09:23:21 1999 +0000
description:
- Sweep machdep.c; mostly imported from a development branch. Little
exposure of TC device any more. Correct comments which are no longer
feasible. Reorder declarations and definitions. Introduce 'clkread'
pointer to pull up model dependent high resolution timer value. Have
prom_systype() call.
- Place routines for model dependent high resolution timer.
- Program IOASIC registers inside os_init() call and nuke ioasic_init().
diffstat:
sys/arch/pmax/pmax/dec_3100.c | 12 +-
sys/arch/pmax/pmax/dec_3max.c | 15 +-
sys/arch/pmax/pmax/dec_3maxplus.c | 47 ++++-
sys/arch/pmax/pmax/dec_3min.c | 68 ++++++-
sys/arch/pmax/pmax/dec_5100.c | 8 +-
sys/arch/pmax/pmax/machdep.c | 321 ++++++++++---------------------------
sys/arch/pmax/pmax/machdep.h | 7 +-
7 files changed, 211 insertions(+), 267 deletions(-)
diffs (truncated from 976 to 300 lines):
diff -r ce3d35b492b6 -r a37d0a29c2d2 sys/arch/pmax/pmax/dec_3100.c
--- a/sys/arch/pmax/pmax/dec_3100.c Mon Apr 26 09:15:59 1999 +0000
+++ b/sys/arch/pmax/pmax/dec_3100.c Mon Apr 26 09:23:21 1999 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: dec_3100.c,v 1.9 1999/04/24 08:01:11 simonb Exp $ */
+/* $NetBSD: dec_3100.c,v 1.10 1999/04/26 09:23:21 nisimura Exp $ */
/*
* Copyright (c) 1998 Jonathan Stone. All rights reserved.
@@ -119,6 +119,8 @@
int (*handler) __P((intr_arg_t)), intr_arg_t arg));
void dec_3100_intr_disestablish __P((struct ibus_attach_args *ia));
+extern unsigned nullclkread __P((void));
+extern unsigned (*clkread) __P((void));
/*
* Fill in platform struct.
@@ -158,6 +160,9 @@
mcclock_addr = (volatile struct chiptime *)
MIPS_PHYS_TO_KSEG1(KN01_SYS_CLOCK);
mc_cpuspeed(mcclock_addr, MIPS_INT_MASK_3);
+
+ /* no high resolution timer circuit; possibly never called */
+ clkread = nullclkread;
}
@@ -239,7 +244,7 @@
}
/* If clock interrupts were enabled, re-enable them ASAP. */
- splx(MIPS_SR_INT_ENA_CUR | (statusReg & MIPS_INT_MASK_3));
+ splx(MIPS_SR_INT_IE | (statusReg & MIPS_INT_MASK_3));
#if NSII > 0
if (mask & MIPS_INT_MASK_0) {
@@ -272,8 +277,7 @@
dec_3100_errintr();
intrcnt[ERROR_INTR]++;
}
- return ((statusReg & ~causeReg & MIPS_HARD_INT_MASK) |
- MIPS_SR_INT_ENA_CUR);
+ return(MIPS_SR_INT_IE | (statusReg & ~causeReg & MIPS_HARD_INT_MASK));
}
void
diff -r ce3d35b492b6 -r a37d0a29c2d2 sys/arch/pmax/pmax/dec_3max.c
--- a/sys/arch/pmax/pmax/dec_3max.c Mon Apr 26 09:15:59 1999 +0000
+++ b/sys/arch/pmax/pmax/dec_3max.c Mon Apr 26 09:23:21 1999 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: dec_3max.c,v 1.9 1999/04/24 08:01:11 simonb Exp $ */
+/* $NetBSD: dec_3max.c,v 1.10 1999/04/26 09:23:22 nisimura Exp $ */
/*
* Copyright (c) 1998 Jonathan Stone. All rights reserved.
@@ -73,7 +73,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: dec_3max.c,v 1.9 1999/04/24 08:01:11 simonb Exp $");
+__KERNEL_RCSID(0, "$NetBSD: dec_3max.c,v 1.10 1999/04/26 09:23:22 nisimura Exp $");
#include <sys/types.h>
#include <sys/systm.h>
@@ -114,6 +114,8 @@
static void dec_3max_errintr __P((void));
+extern unsigned nullclkread __P((void));
+extern unsigned (*clkread) __P((void));
/*
* Fill in platform struct.
@@ -166,9 +168,11 @@
MIPS_PHYS_TO_KSEG1(KN02_SYS_CLOCK);
mc_cpuspeed(mcclock_addr, MIPS_INT_MASK_1);
+
+ /* no high resolution timer circuit; possibly never called */
+ clkread = nullclkread;
}
-
/*
* Initalize the memory system and I/O buses.
*/
@@ -284,7 +288,7 @@
}
/* If clock interrups were enabled, re-enable them ASAP. */
- splx(MIPS_SR_INT_ENA_CUR | (statusReg & MIPS_INT_MASK_1));
+ splx(MIPS_SR_INT_IE | (statusReg & MIPS_INT_MASK_1));
if (mask & MIPS_INT_MASK_0) {
static int intr_map[8] = { SLOT0_INTR, SLOT1_INTR, SLOT2_INTR,
@@ -319,8 +323,7 @@
dec_3max_errintr();
}
- return ((statusReg & ~causeReg & MIPS_HARD_INT_MASK) |
- MIPS_SR_INT_ENA_CUR);
+ return(MIPS_SR_INT_IE | (statusReg & ~causeReg & MIPS_HARD_INT_MASK));
}
diff -r ce3d35b492b6 -r a37d0a29c2d2 sys/arch/pmax/pmax/dec_3maxplus.c
--- a/sys/arch/pmax/pmax/dec_3maxplus.c Mon Apr 26 09:15:59 1999 +0000
+++ b/sys/arch/pmax/pmax/dec_3maxplus.c Mon Apr 26 09:23:21 1999 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: dec_3maxplus.c,v 1.15 1999/04/24 08:01:11 simonb Exp $ */
+/* $NetBSD: dec_3maxplus.c,v 1.16 1999/04/26 09:23:23 nisimura Exp $ */
/*
* Copyright (c) 1998 Jonathan Stone. All rights reserved.
@@ -73,7 +73,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: dec_3maxplus.c,v 1.15 1999/04/24 08:01:11 simonb Exp $");
+__KERNEL_RCSID(0, "$NetBSD: dec_3maxplus.c,v 1.16 1999/04/26 09:23:23 nisimura Exp $");
#include <sys/types.h>
#include <sys/systm.h>
@@ -82,7 +82,6 @@
#include <machine/reg.h>
#include <machine/intr.h>
#include <machine/psl.h>
-#include <machine/locore.h> /* wbflush() */
#include <machine/autoconf.h> /* intr_arg_t */
#include <machine/sysconf.h>
@@ -121,6 +120,9 @@
static void dec_3maxplus_errintr __P ((void));
+void kn03_wbflush __P((void));
+unsigned kn03_clkread __P((void));
+extern unsigned (*clkread) __P((void));
/*
* Local declarations
@@ -170,7 +172,7 @@
/* clear any pending memory errors. */
*(volatile u_int *)MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRADR) = 0;
- wbflush();
+ kn03_wbflush();
/*
* Reset interrupts.
@@ -189,7 +191,6 @@
MIPS_PHYS_TO_KSEG1(KN03_SYS_CLOCK);
mc_cpuspeed(mcclock_addr, MIPS_INT_MASK_1);
- ioasic_init(0);
/*
* Initialize interrupts.
*/
@@ -197,13 +198,24 @@
~(KN03_INTR_TC_0|KN03_INTR_TC_1|KN03_INTR_TC_2);
*(u_int *)IOASIC_REG_IMSK(ioasic_base) = kn03_tc3_imask;
*(u_int *)IOASIC_REG_INTR(ioasic_base) = 0;
- wbflush();
+ kn03_wbflush();
+
+ *(volatile u_int *)(ioasic_base + IOASIC_LANCE_DECODE) = 0x3;
+ *(volatile u_int *)(ioasic_base + IOASIC_SCSI_DECODE) = 0xe;
+#if 0
+ *(volatile u_int *)(ioasic_base + IOASIC_SCC0_DECODE) = (0x10|4);
+ *(volatile u_int *)(ioasic_base + IOASIC_SCC1_DECODE) = (0x10|6);
+ *(volatile u_int *)(ioasic_base + IOASIC_CSR) = 0x00000f00;
+#endif
/* XXX hard-reset LANCE */
- *(u_int *)IOASIC_REG_CSR(ioasic_base) |= 0x100;
+ *(u_int *)IOASIC_REG_CSR(ioasic_base) |= 0x100;
/* clear any memory errors from probes */
*(volatile u_int *)MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRADR) = 0;
- wbflush();
+ kn03_wbflush();
+
+ /* 3MAX+ has IOASIC free-running high resolution timer */
+ clkread = kn03_clkread;
}
@@ -501,3 +513,22 @@
/* Send to kn02/kn03 memory subsystem handler */
dec_mtasic_err(erradr, errsyn);
}
+
+void
+kn03_wbflush()
+{
+ /* read once IOASIC_INTR */
+ __asm __volatile("lw $0,0xbf840000");
+}
+
+/*
+ * TURBOchannel bus-cycle counter provided by IOASIC;
+ * Interpolate micro-seconds since the last RTC clock tick. The
+ * interpolation base is the copy of the bus cycle-counter taken by
+ * the RTC interrupt handler.
+ */
+unsigned
+kn03_clkread()
+{
+ return *(u_int32_t *)(ioasic_base + IOASIC_CTR);
+}
diff -r ce3d35b492b6 -r a37d0a29c2d2 sys/arch/pmax/pmax/dec_3min.c
--- a/sys/arch/pmax/pmax/dec_3min.c Mon Apr 26 09:15:59 1999 +0000
+++ b/sys/arch/pmax/pmax/dec_3min.c Mon Apr 26 09:23:21 1999 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: dec_3min.c,v 1.13 1999/04/24 08:01:11 simonb Exp $ */
+/* $NetBSD: dec_3min.c,v 1.14 1999/04/26 09:23:23 nisimura Exp $ */
/*
* Copyright (c) 1998 Jonathan Stone. All rights reserved.
@@ -73,7 +73,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: dec_3min.c,v 1.13 1999/04/24 08:01:11 simonb Exp $");
+__KERNEL_RCSID(0, "$NetBSD: dec_3min.c,v 1.14 1999/04/26 09:23:23 nisimura Exp $");
#include <sys/types.h>
@@ -83,7 +83,6 @@
#include <machine/intr.h>
#include <machine/reg.h>
#include <machine/psl.h>
-#include <machine/locore.h> /* wbflush() */
#include <machine/autoconf.h> /* intr_arg_t */
#include <machine/sysconf.h>
@@ -131,6 +130,9 @@
int clockmask));
u_long kmin_tc3_imask;
+void kn02ba_wbflush __P((void));
+unsigned kn02ba_clkread __P((void));
+extern unsigned (*clkread) __P((void));
/*
* Fill in platform struct.
@@ -164,10 +166,10 @@
*/
*(volatile u_int *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0;
- wbflush();
+ kn02ba_wbflush();
*(volatile u_int *)IOASIC_REG_INTR(ioasic_base) = 0;
- wbflush();
+ kn02ba_wbflush();
}
@@ -197,6 +199,13 @@
MIPS_PHYS_TO_KSEG1(KMIN_SYS_CLOCK);
dec_3min_mcclock_cpuspeed(mcclock_addr, MIPS_INT_MASK_3);
+ *(volatile u_int *)(ioasic_base + IOASIC_LANCE_DECODE) = 0x3;
+ *(volatile u_int *)(ioasic_base + IOASIC_SCSI_DECODE) = 0xe;
+#if 0
+ *(volatile u_int *)(ioasic_base + IOASIC_SCC0_DECODE) = (0x10|4);
+ *(volatile u_int *)(ioasic_base + IOASIC_SCC1_DECODE) = (0x10|6);
+ *(volatile u_int *)(ioasic_base + IOASIC_CSR) = 0x00000f00;
+#endif
/*
* Initialize interrupts.
*/
@@ -206,7 +215,7 @@
/* clear any memory errors from probes */
*(volatile u_int *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0;
- wbflush();
+ kn02ba_wbflush();
/*
* The kmin memory hardware seems to wrap memory addresses
@@ -223,6 +232,9 @@
* (volatile u_int *)MIPS_PHYS_TO_KSEG1(KMIN_REG_IMSK) =
kmin_tc3_imask |
(KMIN_IM0 & ~(KN03_INTR_TC_0|KN03_INTR_TC_1|KN03_INTR_TC_2));
+
+ /* R4000 3MIN can ultilize on-chip counter */
+ clkread = kn02ba_clkread;
}
@@ -403,8 +415,8 @@
*imaskp = old_mask &
~(KMIN_INTR_SCC_0|KMIN_INTR_SCC_1 |
IOASIC_INTR_LANCE|IOASIC_INTR_SCSI);
- wbflush();
- splx(MIPS_SR_INT_ENA_CUR | (statusReg & MIPS_INT_MASK_3));
+ kn02ba_wbflush();
+ splx(MIPS_SR_INT_IE | (statusReg & MIPS_INT_MASK_3));
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