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[src/trunk]: src/sys/arch Nuke register and remove trailling white space.
details: https://anonhg.NetBSD.org/src/rev/6ac60c15f655
branches: trunk
changeset: 472183:6ac60c15f655
user: simonb <simonb%NetBSD.org@localhost>
date: Sat Apr 24 08:01:01 1999 +0000
description:
Nuke register and remove trailling white space.
diffstat:
sys/arch/mips/conf/files.mips | 4 +-
sys/arch/mips/include/ansi.h | 4 +-
sys/arch/mips/include/asm.h | 10 +-
sys/arch/mips/include/bsd-aout.h | 4 +-
sys/arch/mips/include/cdefs.h | 12 +-
sys/arch/mips/include/cpuregs.h | 10 +-
sys/arch/mips/include/ecoff_machdep.h | 4 +-
sys/arch/mips/include/elf_machdep.h | 4 +-
sys/arch/mips/include/ieeefp.h | 4 +-
sys/arch/mips/include/locore.h | 6 +-
sys/arch/mips/include/mips_param.h | 6 +-
sys/arch/mips/include/pmap.h | 8 +-
sys/arch/mips/include/setjmp.h | 4 +-
sys/arch/mips/include/signal.h | 8 +-
sys/arch/mips/include/stdarg.h | 4 +-
sys/arch/mips/include/types.h | 6 +-
sys/arch/mips/include/vmparam.h | 6 +-
sys/arch/mips/mips/compat_13_machdep.c | 6 +-
sys/arch/mips/mips/cpu_exec.c | 12 +-
sys/arch/mips/mips/db_disasm.c | 6 +-
sys/arch/mips/mips/db_interface.c | 20 +-
sys/arch/mips/mips/db_trace.c | 22 +-
sys/arch/mips/mips/elf.c | 12 +-
sys/arch/mips/mips/in_cksum.c | 60 +++---
sys/arch/mips/mips/locore.S | 14 +-
sys/arch/mips/mips/locore_mips1.S | 18 +-
sys/arch/mips/mips/locore_mips3.S | 48 ++--
sys/arch/mips/mips/mips_machdep.c | 34 +-
sys/arch/mips/mips/mips_mcclock.c | 20 +-
sys/arch/mips/mips/pmap.c | 34 +-
sys/arch/mips/mips/process_machdep.c | 8 +-
sys/arch/mips/mips/sys_machdep.c | 6 +-
sys/arch/mips/mips/trap.c | 80 ++++----
sys/arch/mips/mips/vm_machdep.c | 8 +-
sys/arch/pmax/dev/ascreg.h | 20 +-
sys/arch/pmax/dev/bt459.c | 34 +-
sys/arch/pmax/dev/bt459.h | 22 +-
sys/arch/pmax/dev/bt478.c | 26 +-
sys/arch/pmax/dev/bt478var.h | 4 +-
sys/arch/pmax/dev/cfb.c | 6 +-
sys/arch/pmax/dev/cfbreg.h | 22 +-
sys/arch/pmax/dev/cfbvar.h | 4 +-
sys/arch/pmax/dev/dc.c | 150 +++++++-------
sys/arch/pmax/dev/dc_ds.c | 4 +-
sys/arch/pmax/dev/device.h | 4 +-
sys/arch/pmax/dev/dtop.c | 88 ++++----
sys/arch/pmax/dev/dtopreg.h | 20 +-
sys/arch/pmax/dev/fb.c | 16 +-
sys/arch/pmax/dev/fb_usrreq.c | 22 +-
sys/arch/pmax/dev/fbreg.h | 4 +-
sys/arch/pmax/dev/findcons.c | 16 +-
sys/arch/pmax/dev/ims332.c | 38 +-
sys/arch/pmax/dev/ims332.h | 14 +-
sys/arch/pmax/dev/lk201.c | 62 +++---
sys/arch/pmax/dev/mfb.c | 46 ++--
sys/arch/pmax/dev/mfbreg.h | 14 +-
sys/arch/pmax/dev/mfbvar.h | 4 +-
sys/arch/pmax/dev/pm.c | 34 +-
sys/arch/pmax/dev/pmvar.h | 4 +-
sys/arch/pmax/dev/promio.c | 10 +-
sys/arch/pmax/dev/px.c | 328 ++++++++++++++++----------------
sys/arch/pmax/dev/pxreg.h | 20 +-
sys/arch/pmax/dev/pxvar.h | 12 +-
sys/arch/pmax/dev/qvss_compat.c | 34 +-
sys/arch/pmax/dev/rcons.c | 32 +-
sys/arch/pmax/dev/rconsvar.h | 4 +-
sys/arch/pmax/dev/rz.c | 124 ++++++------
sys/arch/pmax/dev/sccreg.h | 16 +-
sys/arch/pmax/dev/scsi.c | 24 +-
sys/arch/pmax/dev/scsi.h | 23 +-
sys/arch/pmax/dev/sfb.c | 8 +-
sys/arch/pmax/dev/sfbvar.h | 4 +-
sys/arch/pmax/dev/sii.c | 86 ++++----
sys/arch/pmax/dev/sii_ds.c | 28 +-
sys/arch/pmax/dev/tz.c | 48 ++--
sys/arch/pmax/dev/xcfb.c | 18 +-
sys/arch/pmax/dev/xcfbreg.h | 14 +-
sys/arch/pmax/dev/xcfbvar.h | 4 +-
sys/arch/pmax/ibus/ibus_3100.c | 6 +-
sys/arch/pmax/ibus/ibus_5100.c | 8 +-
sys/arch/pmax/ibus/ibusvar.h | 6 +-
sys/arch/pmax/ibus/mcclock_ibus.c | 6 +-
sys/arch/pmax/include/autoconf.h | 12 +-
sys/arch/pmax/include/bootinfo.h | 4 +-
sys/arch/pmax/include/dc7085cons.h | 4 +-
sys/arch/pmax/include/dec_boot.h | 4 +-
sys/arch/pmax/include/dec_exec.h | 8 +-
sys/arch/pmax/include/fbio.h | 10 +-
sys/arch/pmax/include/ieeefp.h | 4 +-
sys/arch/pmax/include/pmioctl.h | 12 +-
sys/arch/pmax/include/sysconf.h | 4 +-
sys/arch/pmax/include/tc_machdep.h | 4 +-
sys/arch/pmax/pmax/autoconf.c | 6 +-
sys/arch/pmax/pmax/conf-glue.c | 8 +-
sys/arch/pmax/pmax/dec_3100.c | 6 +-
sys/arch/pmax/pmax/dec_3max.c | 16 +-
sys/arch/pmax/pmax/dec_3maxplus.c | 18 +-
sys/arch/pmax/pmax/dec_3min.c | 16 +-
sys/arch/pmax/pmax/dec_5100.c | 30 +-
sys/arch/pmax/pmax/dec_kn02_subr.c | 8 +-
sys/arch/pmax/pmax/dec_maxine.c | 12 +-
sys/arch/pmax/pmax/disksubr.c | 12 +-
sys/arch/pmax/pmax/kadb.c | 14 +-
sys/arch/pmax/pmax/machdep.c | 14 +-
sys/arch/pmax/tc/asic.c | 16 +-
sys/arch/pmax/tc/mcclock_ioasic.c | 8 +-
sys/arch/pmax/tc/scc.c | 140 +++++++-------
sys/arch/pmax/tc/tc_3maxplus.c | 7 +-
sys/arch/pmax/tc/tc_subr.c | 18 +-
109 files changed, 1234 insertions(+), 1234 deletions(-)
diffs (truncated from 8127 to 300 lines):
diff -r 810caa2196a5 -r 6ac60c15f655 sys/arch/mips/conf/files.mips
--- a/sys/arch/mips/conf/files.mips Sat Apr 24 07:23:54 1999 +0000
+++ b/sys/arch/mips/conf/files.mips Sat Apr 24 08:01:01 1999 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: files.mips,v 1.19 1999/01/14 18:51:31 castor Exp $
+# $NetBSD: files.mips,v 1.20 1999/04/24 08:10:32 simonb Exp $
#
defopt opt_cputype.h NOTHING_YET # reserved for CPU level
@@ -20,5 +20,5 @@
file arch/mips/mips/in_cksum.c inet
file netns/ns_cksum.c ns
-# Binary compatibility with previous NetBSD releases (COMPAT_XX)
+# Binary compatibility with previous NetBSD releases (COMPAT_XX)
file arch/mips/mips/compat_13_machdep.c compat_13 | compat_ultrix
diff -r 810caa2196a5 -r 6ac60c15f655 sys/arch/mips/include/ansi.h
--- a/sys/arch/mips/include/ansi.h Sat Apr 24 07:23:54 1999 +0000
+++ b/sys/arch/mips/include/ansi.h Sat Apr 24 08:01:01 1999 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: ansi.h,v 1.9 1998/04/27 17:39:11 kleink Exp $ */
+/* $NetBSD: ansi.h,v 1.10 1999/04/24 08:10:33 simonb Exp $ */
/*-
* Copyright (c) 1990, 1993
@@ -69,7 +69,7 @@
* chosen over a long is that the is*() and to*() routines take ints (says
* ANSI C), but they use _RUNE_T_ instead of int. By changing it here, you
* lose a bit of ANSI conformance, but your programs will still work.
- *
+ *
* Note that _WCHAR_T_ and _RUNE_T_ must be of the same type. When wchar_t
* and rune_t are typedef'd, _WCHAR_T_ will be undef'd, but _RUNE_T remains
* defined for ctype.h.
diff -r 810caa2196a5 -r 6ac60c15f655 sys/arch/mips/include/asm.h
--- a/sys/arch/mips/include/asm.h Sat Apr 24 07:23:54 1999 +0000
+++ b/sys/arch/mips/include/asm.h Sat Apr 24 08:01:01 1999 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: asm.h,v 1.21 1999/04/01 09:02:53 soda Exp $ */
+/* $NetBSD: asm.h,v 1.22 1999/04/24 08:10:33 simonb Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -245,7 +245,7 @@
#define NON_LEAF(x, fsize, retpc) NESTED(x, fsize, retpc)
#define NNON_LEAF(x, fsize, retpc) NESTED_NOPROFILE(x, fsize, retpc)
-/*
+/*
* standard callframe {
* register_t cf_args[4]; arg0 - arg3
* register_t cf_sp; frame pointer
@@ -257,11 +257,11 @@
#define CALLFRAME_RA (4 * 5)
/*
- * While it would be nice to be compatible with the SGI
+ * While it would be nice to be compatible with the SGI
* REG_L and REG_S macros, because they do not take parameters, it
* is impossible to use them with the _MIPS_SIM_ABIX32 model.
*
- * These macros hide the use of mips3 instructions from the
+ * These macros hide the use of mips3 instructions from the
* assembler to prevent the assembler from generating 64-bit style
* ABI calls.
*/
@@ -270,7 +270,7 @@
#define REG_L lw
#define REG_S sw
#define REG_LI li
-#define REG_PROLOGUE .set push
+#define REG_PROLOGUE .set push
#define REG_EPILOGUE .set pop
#define SZREG 4
#else
diff -r 810caa2196a5 -r 6ac60c15f655 sys/arch/mips/include/bsd-aout.h
--- a/sys/arch/mips/include/bsd-aout.h Sat Apr 24 07:23:54 1999 +0000
+++ b/sys/arch/mips/include/bsd-aout.h Sat Apr 24 08:01:01 1999 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: bsd-aout.h,v 1.3 1998/01/05 07:03:00 perry Exp $ */
+/* $NetBSD: bsd-aout.h,v 1.4 1999/04/24 08:10:33 simonb Exp $ */
/* bsd-aout.h
@@ -18,7 +18,7 @@
u_short a_magic; /* magic number */
u_short a_mid; /* machine ID */
#endif
-
+
u_long a_text; /* text segment size */
u_long a_data; /* initialized data size */
u_long a_bss; /* uninitialized data size */
diff -r 810caa2196a5 -r 6ac60c15f655 sys/arch/mips/include/cdefs.h
--- a/sys/arch/mips/include/cdefs.h Sat Apr 24 07:23:54 1999 +0000
+++ b/sys/arch/mips/include/cdefs.h Sat Apr 24 08:01:01 1999 +0000
@@ -1,21 +1,21 @@
-/* $NetBSD: cdefs.h,v 1.10 1999/03/20 01:40:26 thorpej Exp $ */
+/* $NetBSD: cdefs.h,v 1.11 1999/04/24 08:10:34 simonb Exp $ */
/*
* Copyright (c) 1995 Carnegie-Mellon University.
* All rights reserved.
*
* Author: Chris G. Demetriou
- *
+ *
* Permission to use, copy, modify and distribute this software and
* its documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
- *
- * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
- * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
+ *
+ * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
+ * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
- *
+ *
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution%CS.CMU.EDU@localhost
diff -r 810caa2196a5 -r 6ac60c15f655 sys/arch/mips/include/cpuregs.h
--- a/sys/arch/mips/include/cpuregs.h Sat Apr 24 07:23:54 1999 +0000
+++ b/sys/arch/mips/include/cpuregs.h Sat Apr 24 08:01:01 1999 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuregs.h,v 1.19 1999/01/23 06:13:30 nisimura Exp $ */
+/* $NetBSD: cpuregs.h,v 1.20 1999/04/24 08:10:34 simonb Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -295,7 +295,7 @@
(((config) & (bit)) ? 32 : 16)
#define MIPS3_CONFIG_DC_MASK 0x000001c0 /* Primary D-cache size */
-#define MIPS3_CONFIG_DC_SHIFT 6
+#define MIPS3_CONFIG_DC_SHIFT 6
#define MIPS3_CONFIG_IC_MASK 0x00000e00 /* Primary I-cache size */
#define MIPS3_CONFIG_IC_SHIFT 9
#define MIPS3_CONFIG_CACHE_SIZE(config, mask, shift) \
@@ -548,7 +548,7 @@
/*
* r3000: shift count to put the index in the right spot.
- * (zero on r4000?)
+ * (zero on r4000?)
*/
#define MIPS1_TLB_INDEX_SHIFT 8
@@ -572,7 +572,7 @@
/*
* backwards compatibility with existing locore and compile-time
- * mips1/mips3 binding.
+ * mips1/mips3 binding.
*
* XXX INT_MASK and HARD_INT_MASK are here only because we dont
* support the mips3 on-chip timer which is tied to INT_5.
@@ -615,7 +615,7 @@
#define MIPS_R4000 0x04 /* MIPS R4000/4400 CPU ISA III */
#define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivate ISA I */
#define MIPS_R6000A 0x06 /* MIPS R6000A CPU ISA II */
-#define MIPS_R3IDT 0x07 /* IDT R3041 or RC36100 CPU ISA I */
+#define MIPS_R3IDT 0x07 /* IDT R3041 or RC36100 CPU ISA I */
#define MIPS_R10000 0x09 /* MIPS R10000/T5 CPU ISA IV */
#define MIPS_R4200 0x0a /* NEC VR4200 CPU ISA III */
#define MIPS_R4300 0x0b /* NEC VR4300 CPU ISA III */
diff -r 810caa2196a5 -r 6ac60c15f655 sys/arch/mips/include/ecoff_machdep.h
--- a/sys/arch/mips/include/ecoff_machdep.h Sat Apr 24 07:23:54 1999 +0000
+++ b/sys/arch/mips/include/ecoff_machdep.h Sat Apr 24 08:01:01 1999 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: ecoff_machdep.h,v 1.15 1999/03/08 06:36:59 tsubai Exp $ */
+/* $NetBSD: ecoff_machdep.h,v 1.16 1999/04/24 08:10:34 simonb Exp $ */
/*
* Copyright (c) 1997 Jonathan Stone
@@ -49,7 +49,7 @@
#define _MIPS3_OK() 1
#endif
-
+
#define ECOFF_MAGIC_MIPSEB 0x0160 /* mips1, big-endian */
#define ECOFF_MAGIC_MIPSEL 0x0162 /* mips1, little-endian */
#define ECOFF_MAGIC_MIPSEL3 0x0142 /* mips3, little-endian */
diff -r 810caa2196a5 -r 6ac60c15f655 sys/arch/mips/include/elf_machdep.h
--- a/sys/arch/mips/include/elf_machdep.h Sat Apr 24 07:23:54 1999 +0000
+++ b/sys/arch/mips/include/elf_machdep.h Sat Apr 24 08:01:01 1999 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: elf_machdep.h,v 1.4 1998/03/25 04:06:50 mhitch Exp $ */
+/* $NetBSD: elf_machdep.h,v 1.5 1999/04/24 08:10:35 simonb Exp $ */
#define ELF32_MACHDEP_ID_CASES \
case Elf_em_mips: \
@@ -32,7 +32,7 @@
#define R_MIPS_UNUSED2 14
#define R_MIPS_UNUSED3 15
-/*
+/*
* The remaining relocs are apparently part of the 64-bit Irix ELF ABI.
*/
#define R_MIPS_SHIFT5 16
diff -r 810caa2196a5 -r 6ac60c15f655 sys/arch/mips/include/ieeefp.h
--- a/sys/arch/mips/include/ieeefp.h Sat Apr 24 07:23:54 1999 +0000
+++ b/sys/arch/mips/include/ieeefp.h Sat Apr 24 08:01:01 1999 +0000
@@ -1,6 +1,6 @@
-/* $NetBSD: ieeefp.h,v 1.3 1998/01/05 07:03:01 perry Exp $ */
+/* $NetBSD: ieeefp.h,v 1.4 1999/04/24 08:10:35 simonb Exp $ */
-/*
+/*
* Written by J.T. Conklin, Apr 11, 1995
* Public domain.
*/
diff -r 810caa2196a5 -r 6ac60c15f655 sys/arch/mips/include/locore.h
--- a/sys/arch/mips/include/locore.h Sat Apr 24 07:23:54 1999 +0000
+++ b/sys/arch/mips/include/locore.h Sat Apr 24 08:01:01 1999 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.h,v 1.19 1999/02/27 02:54:05 jonathan Exp $ */
+/* $NetBSD: locore.h,v 1.20 1999/04/24 08:10:35 simonb Exp $ */
/*
* Copyright 1996 The Board of Trustees of The Leland Stanford
@@ -19,7 +19,7 @@
* archtecture (ISA) level, the Mips family.
* The following functions must be provided for each mips ISA level:
*
- *
+ *
* MachFlushCache
* MachFlushDCache
* MachFlushICache
@@ -230,7 +230,7 @@
#endif /* MIPS3 */
/*
- * trapframe argument passed to trap()
+ * trapframe argument passed to trap()
*/
struct trapframe {
mips_reg_t tf_regs[17];
diff -r 810caa2196a5 -r 6ac60c15f655 sys/arch/mips/include/mips_param.h
--- a/sys/arch/mips/include/mips_param.h Sat Apr 24 07:23:54 1999 +0000
+++ b/sys/arch/mips/include/mips_param.h Sat Apr 24 08:01:01 1999 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: mips_param.h,v 1.12 1999/02/09 17:15:52 tv Exp $ */
+/* $NetBSD: mips_param.h,v 1.13 1999/04/24 08:10:36 simonb Exp $ */
/*
* NOTE: SSIZE, SINCR and UPAGES must be multiples of CLSIZE.
@@ -24,7 +24,7 @@
* ALIGNED_POINTER is a boolean macro that checks whether an address
* is valid to fetch data elements of type t from on this architecture.
* This does not reflect the optimal alignment, just the possibility
- * (within reasonable limits).
+ * (within reasonable limits).
*
*/
#define ALIGNBYTES 7
@@ -42,7 +42,7 @@
/*
* Size of kernel malloc arena in CLBYTES-sized logical pages
- */
+ */
#ifndef NKMEMCLUSTERS
#define NKMEMCLUSTERS (6 * 1024 * 1024 / CLBYTES)
#endif
diff -r 810caa2196a5 -r 6ac60c15f655 sys/arch/mips/include/pmap.h
--- a/sys/arch/mips/include/pmap.h Sat Apr 24 07:23:54 1999 +0000
+++ b/sys/arch/mips/include/pmap.h Sat Apr 24 08:01:01 1999 +0000
@@ -1,6 +1,6 @@
-/* $NetBSD: pmap.h,v 1.25 1999/02/26 19:03:39 is Exp $ */
+/* $NetBSD: pmap.h,v 1.26 1999/04/24 08:10:36 simonb Exp $ */
-/*
+/*
* Copyright (c) 1987 Carnegie-Mellon University
* Copyright (c) 1992, 1993
* The Regents of the University of California. All rights reserved.
@@ -55,7 +55,7 @@
* The user address space is mapped using a two level structure where
* virtual address bits 30..22 are used to index into a segment table which
* points to a page worth of PTEs (4096 page can hold 1024 PTEs).
- * Bits 21..12 are then used to index a PTE which describes a page within
+ * Bits 21..12 are then used to index a PTE which describes a page within
* a segment.
*
* The wired entries in the TLB will contain the following:
@@ -144,7 +144,7 @@
#define PMAP_UNMAP_POOLPAGE(va) MIPS_KSEG0_TO_PHYS((va))
/*
- * Kernel cache operations for the user-space API
+ * Kernel cache operations for the user-space API
*/
int mips_user_cacheflush __P((struct proc *p, vaddr_t va, int nbytes,
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