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[src/trunk]: src/sys/arch/arm/ti Add I2C support.
details: https://anonhg.NetBSD.org/src/rev/515d1efe388a
branches: trunk
changeset: 460542:515d1efe388a
user: jmcneill <jmcneill%NetBSD.org@localhost>
date: Sun Oct 27 19:11:07 2019 +0000
description:
Add I2C support.
diffstat:
sys/arch/arm/ti/am3_prcm.c | 8 +-
sys/arch/arm/ti/files.ti | 7 +-
sys/arch/arm/ti/ti_iic.c | 629 ++++++++++++++++++++++++++++++++++++++++++++
sys/arch/arm/ti/ti_iicreg.h | 143 ++++++++++
4 files changed, 784 insertions(+), 3 deletions(-)
diffs (truncated from 830 to 300 lines):
diff -r 4f7c1bb6574e -r 515d1efe388a sys/arch/arm/ti/am3_prcm.c
--- a/sys/arch/arm/ti/am3_prcm.c Sun Oct 27 19:10:38 2019 +0000
+++ b/sys/arch/arm/ti/am3_prcm.c Sun Oct 27 19:11:07 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: am3_prcm.c,v 1.3 2019/10/27 16:31:26 jmcneill Exp $ */
+/* $NetBSD: am3_prcm.c,v 1.4 2019/10/27 19:11:07 jmcneill Exp $ */
/*-
* Copyright (c) 2017 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -28,7 +28,7 @@
#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: am3_prcm.c,v 1.3 2019/10/27 16:31:26 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: am3_prcm.c,v 1.4 2019/10/27 19:11:07 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -97,6 +97,10 @@
AM3_PRCM_HWMOD_PER("uart4", 0x78, "PERIPH_CLK"),
AM3_PRCM_HWMOD_PER("uart5", 0x38, "PERIPH_CLK"),
+ AM3_PRCM_HWMOD_WKUP("i2c1", 0xb8, "PERIPH_CLK"),
+ AM3_PRCM_HWMOD_PER("i2c2", 0x48, "PERIPH_CLK"),
+ AM3_PRCM_HWMOD_PER("i2c3", 0x44, "PERIPH_CLK"),
+
AM3_PRCM_HWMOD_WKUP("timer0", 0x10, "FIXED_32K"),
AM3_PRCM_HWMOD_PER("timer2", 0x80, "PERIPH_CLK"),
AM3_PRCM_HWMOD_PER("timer3", 0x84, "PERIPH_CLK"),
diff -r 4f7c1bb6574e -r 515d1efe388a sys/arch/arm/ti/files.ti
--- a/sys/arch/arm/ti/files.ti Sun Oct 27 19:10:38 2019 +0000
+++ b/sys/arch/arm/ti/files.ti Sun Oct 27 19:11:07 2019 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: files.ti,v 1.10 2019/10/27 16:31:26 jmcneill Exp $
+# $NetBSD: files.ti,v 1.11 2019/10/27 19:11:07 jmcneill Exp $
#
file arch/arm/ti/ti_platform.c soc_ti
@@ -31,6 +31,11 @@
attach omaptimer at fdt
file arch/arm/ti/ti_omaptimer.c omaptimer
+# I2C
+device tiiic: i2cbus, i2cexec
+attach tiiic at fdt with ti_iic
+file arch/arm/ti/ti_iic.c ti_iic
+
# Ethernet
device cpsw: ether, ifnet, arp, mii, mii_phy
attach cpsw at fdt
diff -r 4f7c1bb6574e -r 515d1efe388a sys/arch/arm/ti/ti_iic.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/ti/ti_iic.c Sun Oct 27 19:11:07 2019 +0000
@@ -0,0 +1,629 @@
+/* $NetBSD: ti_iic.c,v 1.1 2019/10/27 19:11:07 jmcneill Exp $ */
+
+/*
+ * Copyright (c) 2013 Manuel Bouyer. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*-
+ * Copyright (c) 2012 Jared D. McNeill <jmcneill%invisible.ca@localhost>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: ti_iic.c,v 1.1 2019/10/27 19:11:07 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+#include <sys/conf.h>
+#include <sys/bus.h>
+#include <sys/proc.h>
+#include <sys/kernel.h>
+#include <sys/mutex.h>
+#include <sys/condvar.h>
+
+#include <dev/i2c/i2cvar.h>
+
+#include <dev/fdt/fdtvar.h>
+
+#include <arm/ti/ti_prcm.h>
+#include <arm/ti/ti_iicreg.h>
+
+#ifndef OMAP2_I2C_SLAVE_ADDR
+#define OMAP2_I2C_SLAVE_ADDR 0x01
+#endif
+
+#define OMAP2_I2C_FIFOBYTES(fd) (8 << (fd))
+
+#ifdef I2CDEBUG
+#define DPRINTF(args) printf args
+#else
+#define DPRINTF(args)
+#endif
+
+static const char * compatible [] = {
+ "ti,omap4-i2c",
+ NULL
+};
+
+/* operation in progress */
+typedef enum {
+ TI_I2CREAD,
+ TI_I2CWRITE,
+ TI_I2CDONE,
+ TI_I2CERROR
+} ti_i2cop_t;
+
+struct ti_iic_softc {
+ device_t sc_dev;
+ struct i2c_controller sc_ic;
+ kmutex_t sc_lock;
+ device_t sc_i2cdev;
+
+ bus_space_tag_t sc_iot;
+ bus_space_handle_t sc_ioh;
+
+ void *sc_ih;
+ kmutex_t sc_mtx;
+ kcondvar_t sc_cv;
+ ti_i2cop_t sc_op;
+ int sc_buflen;
+ int sc_bufidx;
+ char *sc_buf;
+
+ bool sc_busy;
+
+ int sc_rxthres;
+ int sc_txthres;
+};
+
+#define I2C_READ_REG(sc, reg) \
+ bus_space_read_2((sc)->sc_iot, (sc)->sc_ioh, (reg))
+#define I2C_READ_DATA(sc) \
+ bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, OMAP2_I2C_DATA);
+#define I2C_WRITE_REG(sc, reg, val) \
+ bus_space_write_2((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
+#define I2C_WRITE_DATA(sc, val) \
+ bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, OMAP2_I2C_DATA, (val))
+
+static int ti_iic_match(device_t, cfdata_t, void *);
+static void ti_iic_attach(device_t, device_t, void *);
+
+static int ti_iic_intr(void *);
+
+static int ti_iic_acquire_bus(void *, int);
+static void ti_iic_release_bus(void *, int);
+static int ti_iic_exec(void *, i2c_op_t, i2c_addr_t, const void *,
+ size_t, void *, size_t, int);
+
+static int ti_iic_reset(struct ti_iic_softc *);
+static int ti_iic_op(struct ti_iic_softc *, i2c_addr_t, ti_i2cop_t,
+ uint8_t *, size_t, int);
+static void ti_iic_handle_intr(struct ti_iic_softc *, uint32_t);
+static void ti_iic_do_read(struct ti_iic_softc *, uint32_t);
+static void ti_iic_do_write(struct ti_iic_softc *, uint32_t);
+
+static int ti_iic_wait(struct ti_iic_softc *, uint16_t, uint16_t, int);
+static uint32_t ti_iic_stat(struct ti_iic_softc *, uint32_t);
+static int ti_iic_flush(struct ti_iic_softc *);
+
+static i2c_tag_t ti_iic_get_tag(device_t);
+
+static const struct fdtbus_i2c_controller_func ti_iic_funcs = {
+ .get_tag = ti_iic_get_tag,
+};
+
+CFATTACH_DECL_NEW(ti_iic, sizeof(struct ti_iic_softc),
+ ti_iic_match, ti_iic_attach, NULL, NULL);
+
+static int
+ti_iic_match(device_t parent, cfdata_t match, void *opaque)
+{
+ struct fdt_attach_args * const faa = opaque;
+
+ return of_match_compatible(faa->faa_phandle, compatible);
+}
+
+static void
+ti_iic_attach(device_t parent, device_t self, void *opaque)
+{
+ struct ti_iic_softc *sc = device_private(self);
+ struct fdt_attach_args * const faa = opaque;
+ const int phandle = faa->faa_phandle;
+ int scheme, major, minor, fifodepth, fifo;
+ char intrstr[128];
+ bus_addr_t addr;
+ bus_size_t size;
+ uint16_t rev;
+
+ if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
+ aprint_error(": couldn't get registers\n");
+ return;
+ }
+ if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) {
+ aprint_error(": couldn't decode interrupt\n");
+ return;
+ }
+
+ if (ti_prcm_enable_hwmod(OF_parent(phandle), 0) != 0) {
+ aprint_error(": couldn't enable module\n");
+ return;
+ }
+
+ sc->sc_dev = self;
+ sc->sc_iot = faa->faa_bst;
+ mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE);
+ mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_NET);
+ cv_init(&sc->sc_cv, "tiiic");
+ sc->sc_ic.ic_cookie = sc;
+ sc->sc_ic.ic_acquire_bus = ti_iic_acquire_bus;
+ sc->sc_ic.ic_release_bus = ti_iic_release_bus;
+ sc->sc_ic.ic_exec = ti_iic_exec;
+
+ if (bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh) != 0) {
+ aprint_error(": couldn't map registers\n");
+ return;
+ }
+
+ sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_NET, 0,
+ ti_iic_intr, sc);
+ if (sc->sc_ih == NULL) {
+ aprint_error(": couldn't establish interrupt\n");
+ return;
+ }
+
+ scheme = I2C_REVNB_HI_SCHEME(I2C_READ_REG(sc, OMAP2_I2C_REVNB_HI));
+ rev = I2C_READ_REG(sc, OMAP2_I2C_REVNB_LO);
+ if (scheme == 0) {
+ major = I2C_REV_SCHEME_0_MAJOR(rev);
+ minor = I2C_REV_SCHEME_0_MINOR(rev);
+ } else {
+ major = I2C_REVNB_LO_MAJOR(rev);
+ minor = I2C_REVNB_LO_MINOR(rev);
+ }
+ aprint_normal(": rev %d.%d, scheme %d\n", major, minor, scheme);
+ aprint_naive("\n");
+
+ fifodepth = I2C_BUFSTAT_FIFODEPTH(I2C_READ_REG(sc, OMAP2_I2C_BUFSTAT));
+ fifo = OMAP2_I2C_FIFOBYTES(fifodepth);
+ aprint_normal_dev(self, "%d-bytes FIFO\n", fifo);
+ sc->sc_rxthres = sc->sc_txthres = fifo >> 1;
+
+ ti_iic_reset(sc);
+ ti_iic_flush(sc);
+
+ fdtbus_register_i2c_controller(self, phandle, &ti_iic_funcs);
+
+ fdtbus_attach_i2cbus(self, phandle, &sc->sc_ic, iicbus_print);
+}
+
+static int
+ti_iic_intr(void *arg)
+{
+ struct ti_iic_softc *sc = arg;
+ uint32_t stat;
+
+ mutex_enter(&sc->sc_mtx);
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