[src/trunk]: src/sys/dev/ic define SSD1322 command set

[tnn <tnn%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/bce71d971d4c
branches:  trunk
changeset: 460423:bce71d971d4c
user:      tnn <tnn%NetBSD.org@localhost>
date:      Tue Oct 22 21:40:10 2019 +0000

description:
define SSD1322 command set

diffstat:

 sys/dev/ic/ssdfbvar.h |  83 +++++++++++++++++++++++++++++++++++++++++++++-----
 1 files changed, 74 insertions(+), 9 deletions(-)

diffs (116 lines):

diff -r 86d759f8179e -r bce71d971d4c sys/dev/ic/ssdfbvar.h
--- a/sys/dev/ic/ssdfbvar.h     Tue Oct 22 18:43:14 2019 +0000
+++ b/sys/dev/ic/ssdfbvar.h     Tue Oct 22 21:40:10 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: ssdfbvar.h,v 1.2 2019/03/17 04:03:17 tnn Exp $ */
+/* $NetBSD: ssdfbvar.h,v 1.3 2019/10/22 21:40:10 tnn Exp $ */
 
 /*
  * Copyright (c) 2019 The NetBSD Foundation, Inc.
@@ -101,15 +101,11 @@
  * SH1106 Rev 0.1 p.24,25,26
  */
 #define SSDFB_CMD_SET_DISPLAY_CLOCK_RATIO              0xd5
-       #define SSDFB_DISPLAY_CLOCK_DIVIDER_MASK        0x0f
-       #define SSDFB_DISPLAY_CLOCK_DIVIDER_SHIFT       0
-       #define SSDFB_DISPLAY_CLOCK_OSCILLATOR_MASK     0xf0
-       #define SSDFB_DISPLAY_CLOCK_OSCILLATOR_SHIFT    4
+       #define SSDFB_DISPLAY_CLOCK_DIVIDER_MASK        __BITS(3, 0)
+       #define SSDFB_DISPLAY_CLOCK_OSCILLATOR_MASK     __BITS(7, 4)
 #define SSDFB_CMD_SET_PRECHARGE_PERIOD                 0xd9
-       #define SSDFB_PRECHARGE_MASK                    0x0f
-       #define SSDFB_PRECHARGE_SHIFT                   0
-       #define SSDFB_DISCHARGE_MASK                    0xf0
-       #define SSDFB_DISCHARGE_SHIFT                   4
+       #define SSDFB_PRECHARGE_MASK                    __BITS(3, 0)
+       #define SSDFB_DISCHARGE_MASK                    __BITS(7, 4)
 #define SSDFB_CMD_SET_VCOMH_DESELECT_LEVEL             0xdb
        #define SSD1306_VCOMH_DESELECT_LEVEL_0_65_VCC   0x00
        #define SSD1306_VCOMH_DESELECT_LEVEL_0_77_VCC   0x20
@@ -146,10 +142,78 @@
        #define SH1106_DC_DC_OFF                        0x8a
        #define SH1106_DC_DC_ON                         0x8b
 
+/*
+ * SSD1322 command set
+ */
+#define SSD1322_CMD_ENABLE_GRAY_SCALE_TABLE            0x00
+#define SSD1322_CMD_SET_COLUMN_ADDRESS                 0x15
+#define SSD1322_CMD_WRITE_RAM                          0x5c
+#define SSD1322_CMD_READ_RAM                           0x5d
+#define SSD1322_CMD_SET_ROW_ADDRESS                    0x75
+#define SSD1322_CMD_SET_REMAP_AND_DUAL_COM_LINE_MODE   0xa0
+#define SSD1322_CMD_SET_DISPLAY_START_LINE             0xa1
+#define SSD1322_CMD_SET_DISPLAY_OFFSET                 0xa2
+
+/* These are the same as SSDFB generic commands */
+#define SSD1322_CMD_ENTIRE_DISPLAY_OFF                 0xa4
+#define SSD1322_CMD_ENTIRE_DISPLAY_ON                  0xa5
+#define SSD1322_CMD_NORMAL_DISPLAY                     0xa6
+#define SSD1322_CMD_INVERSE_DISPLAY                    0xa7
+
+#define SSD1322_CMD_ENABLE_PARTIAL_DISPLAY             0xa8
+#define SSD1322_CMD_EXIT_PARTIAL_DISPLAY               0xa9
+#define SSD1322_CMD_FUNCTION_SELECTION                 0xab
+       #define SSD1322_FUNCTION_SELECTION_EXTERNAL_VDD 0
+       #define SSD1322_FUNCTION_SELECTION_INTERNAL_VDD __BIT(0)
+#define SSD1322_CMD_SET_SLEEP_MODE_ON                  0xae
+#define SSD1322_CMD_SET_SLEEP_MODE_OFF                 0xaf
+#define SSD1322_CMD_SET_PHASE_LENGTH                   0xb1
+       #define SSD1322_PHASE_LENGTH_PHASE_2_MASK       __BITS(7, 4)
+       #define SSD1322_DEFAULT_PHASE_2                 7
+       #define SSD1322_PHASE_LENGTH_PHASE_1_MASK       __BITS(3, 0)
+       #define SSD1322_DEFAULT_PHASE_1                 4
+#define SSD1322_CMD_SET_FRONT_CLOCK_DIVIDER            0xb3
+       #define SSD1322_FREQUENCY_MASK                  __BITS(7, 4)
+       #define SSD1322_DEFAULT_FREQUENCY               5
+       #define SSD1322_DIVIDER_MASK                    __BITS(3, 0)
+       #define SSD1322_DEFAULT_DIVIDER                 0
+#define SSD1322_CMD_DISPLAY_ENHANCEMENT_A              0xb4
+       #define SSD1322_DISPLAY_ENHANCEMENT_A_MAGIC1    0xa2
+       #define SSD1322_DISPLAY_ENHANCEMENT_A_MAGIC2    0xb5
+#define SSD1322_CMD_SET_GPIO                           0xb5
+       #define SSD1322_GPIO0_DISABLED                  0
+       #define SSD1322_GPIO0_TRISTATE                  __BIT(0)
+       #define SSD1322_GPIO0_LOW                       __BIT(1)
+       #define SSD1322_GPIO0_HIGH                      __BITS(1, 0)
+       #define SSD1322_GPIO1_DISABLED                  0
+       #define SSD1322_GPIO1_TRISTATE                  __BIT(2)
+       #define SSD1322_GPIO1_LOW                       __BIT(3)
+       #define SSD1322_GPIO1_HIGH                      __BITS(3, 2)
+#define SSD1322_CMD_SET_SECOND_PRECHARGE_PERIOD                0xb6
+       #define SSD1322_DEFAULT_SECOND_PRECHARGE        8
+#define SSD1322_CMD_SET_GRAY_SCALE_TABLE               0xb8
+#define SSD1322_CMD_SET_DEFAULT_GRAY_SCALE_TABLE       0xb9
+#define SSD1322_CMD_SET_PRE_CHARGE_VOLTAGE_LEVEL       0xbb
+       #define SSD1322_DEFAULT_PRE_CHARGE_VOLTAGE_LEVEL        0x17
+#define SSD1322_CMD_SET_VCOMH                          0xbe
+       #define SSD1322_DEFAULT_VCOMH                   0x04
+#define SSD1322_CMD_SET_CONTRAST_CURRENT               0xc1
+       #define SSD1322_DEFAULT_CONTRAST_CURRENT        0x7f
+#define SSD1322_CMD_MASTER_CONTRAST_CURRENT_CONTROL    0xc7
+       #define SSD1322_DEFAULT_MASTER_CONTRAST_CURRENT_CONTROL 0xf
+#define SSD1322_CMD_SET_MUX_RATIO                      0xca
+#define SSD1322_CMD_DISPLAY_ENHANCEMENT_B              0xd1
+       #define SSD1322_DISPLAY_ENHANCEMENT_B_MAGIC1    0xa2
+       #define SSD1322_DISPLAY_ENHANCEMENT_B_MAGIC2    0x20
+#define SSD1322_CMD_SET_COMMAND_LOCK                   0xfd
+       #define SSD1322_COMMAND_UNLOCK_MAGIC            0x12
+       #define SSD1322_COMMAND_LOCK_MAGIC              0x16
+
 typedef enum {
        SSDFB_CONTROLLER_UNKNOWN=0,
        SSDFB_CONTROLLER_SSD1306=1,
        SSDFB_CONTROLLER_SH1106=2,
+       SSDFB_CONTROLLER_SSD1322=3,
 } ssdfb_controller_id_t;
 
 typedef enum {
@@ -158,6 +222,7 @@
        SSDFB_PRODUCT_SH1106_GENERIC=2,
        SSDFB_PRODUCT_ADAFRUIT_931=3,
        SSDFB_PRODUCT_ADAFRUIT_938=4,
+       SSDFB_PRODUCT_SSD1322_GENERIC=5,
 } ssdfb_product_id_t;
 
 #define SSDFB_I2C_DEFAULT_ADDR         0x3c