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[src/trunk]: src/external/gpl3/gcc/dist/gcc/config merge GCC 8.3.



details:   https://anonhg.NetBSD.org/src/rev/d77015d92a42
branches:  trunk
changeset: 459932:d77015d92a42
user:      mrg <mrg%NetBSD.org@localhost>
date:      Tue Oct 01 22:44:18 2019 +0000

description:
merge GCC 8.3.

XXX: our change for e500 has moved into 'powerpcspe' port, which has
XXX: been marked deprecated in GCC 8.  this may affect what ppc ports
XXX: can update to GCC 8 easily, and we may need to add support for
XXX: 'powerpcspe' while we can.

diffstat:

 external/gpl3/gcc/dist/gcc/config/powerpcspe/powerpcspe.c |      5 +-
 external/gpl3/gcc/dist/gcc/config/rs6000/rs6000.c         |  11353 ++++-------
 2 files changed, 3851 insertions(+), 7507 deletions(-)

diffs (truncated from 16332 to 300 lines):

diff -r fef5c44b684d -r d77015d92a42 external/gpl3/gcc/dist/gcc/config/powerpcspe/powerpcspe.c
--- a/external/gpl3/gcc/dist/gcc/config/powerpcspe/powerpcspe.c Tue Oct 01 22:41:59 2019 +0000
+++ b/external/gpl3/gcc/dist/gcc/config/powerpcspe/powerpcspe.c Tue Oct 01 22:44:18 2019 +0000
@@ -4369,7 +4369,10 @@
      load/store multiple and string instructions.  */
   if (BYTES_BIG_ENDIAN && optimize_size && rs6000_gen_cell_microcode)
     rs6000_isa_flags |= ~rs6000_isa_flags_explicit & (OPTION_MASK_MULTIPLE
-                                                     | OPTION_MASK_STRING);
+#if !defined (POWERPC_NETBSD)
+                                                     | OPTION_MASK_STRING
+#endif
+                                                     );
 
   /* Don't allow -mmultiple or -mstring on little endian systems
      unless the cpu is a 750, because the hardware doesn't support the
diff -r fef5c44b684d -r d77015d92a42 external/gpl3/gcc/dist/gcc/config/rs6000/rs6000.c
--- a/external/gpl3/gcc/dist/gcc/config/rs6000/rs6000.c Tue Oct 01 22:41:59 2019 +0000
+++ b/external/gpl3/gcc/dist/gcc/config/rs6000/rs6000.c Tue Oct 01 22:44:18 2019 +0000
@@ -18,6 +18,8 @@
    along with GCC; see the file COPYING3.  If not see
    <http://www.gnu.org/licenses/>.  */
 
+#define IN_TARGET_CODE 1
+
 #include "config.h"
 #include "system.h"
 #include "coretypes.h"
@@ -42,6 +44,7 @@
 #include "flags.h"
 #include "alias.h"
 #include "fold-const.h"
+#include "attribs.h"
 #include "stor-layout.h"
 #include "calls.h"
 #include "print-tree.h"
@@ -55,6 +58,7 @@
 #include "reload.h"
 #include "sched-int.h"
 #include "gimplify.h"
+#include "gimple-fold.h"
 #include "gimple-iterator.h"
 #include "gimple-ssa.h"
 #include "gimple-walk.h"
@@ -64,6 +68,7 @@
 #include "tree-vectorizer.h"
 #include "target-globals.h"
 #include "builtins.h"
+#include "tree-vector-builder.h"
 #include "context.h"
 #include "tree-pass.h"
 #include "except.h"
@@ -75,6 +80,9 @@
 #endif
 #include "case-cfn-macros.h"
 #include "ppc-auxv.h"
+#include "tree-ssa-propagate.h"
+#include "tree-vrp.h"
+#include "tree-ssanames.h"
 
 /* This file should be included last.  */
 #include "target-def.h"
@@ -83,9 +91,25 @@
 #define TARGET_NO_PROTOTYPE 0
 #endif
 
+  /* Set -mabi=ieeelongdouble on some old targets.  In the future, power server
+     systems will also set long double to be IEEE 128-bit.  AIX and Darwin
+     explicitly redefine TARGET_IEEEQUAD and TARGET_IEEEQUAD_DEFAULT to 0, so
+     those systems will not pick up this default.  This needs to be after all
+     of the include files, so that POWERPC_LINUX and POWERPC_FREEBSD are
+     properly defined.  */
+#ifndef TARGET_IEEEQUAD_DEFAULT
+#if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
+#define TARGET_IEEEQUAD_DEFAULT 1
+#else
+#define TARGET_IEEEQUAD_DEFAULT 0
+#endif
+#endif
+
 #define min(A,B)       ((A) < (B) ? (A) : (B))
 #define max(A,B)       ((A) > (B) ? (A) : (B))
 
+static pad_direction rs6000_function_arg_padding (machine_mode, const_tree);
+
 /* Structure used to define the rs6000 stack */
 typedef struct rs6000_stack {
   int reload_completed;                /* stack info won't change from here on */
@@ -106,7 +130,6 @@
   int lr_save_offset;          /* offset to save LR from initial SP */
   int cr_save_offset;          /* offset to save CR from initial SP */
   int vrsave_save_offset;      /* offset to save VRSAVE from initial SP */
-  int spe_gp_save_offset;      /* offset to save spe 64-bit gprs  */
   int varargs_save_offset;     /* offset to save the varargs registers */
   int ehrd_offset;             /* offset to EH return data */
   int ehcr_offset;             /* offset to EH CR field data */
@@ -121,10 +144,7 @@
   int cr_size;                 /* size to hold CR if not in fixed area */
   int vrsave_size;             /* size to hold VRSAVE */
   int altivec_padding_size;    /* size of altivec alignment padding */
-  int spe_gp_size;             /* size of 64-bit GPR save size for SPE */
-  int spe_padding_size;
   HOST_WIDE_INT total_size;    /* total bytes allocated for stack */
-  int spe_64bit_regs_used;
   int savres_strategy;
 } rs6000_stack_t;
 
@@ -132,8 +152,6 @@
    This is added to the cfun structure.  */
 typedef struct GTY(()) machine_function
 {
-  /* Whether the instruction chain has been scanned already.  */
-  int spe_insn_chain_scanned_p;
   /* Flags if __builtin_return_address (n) with n >= 1 was used.  */
   int ra_needs_full_frame;
   /* Flags if __builtin_return_address (0) was used.  */
@@ -146,19 +164,19 @@
   /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
      varargs save area.  */
   HOST_WIDE_INT varargs_save_offset;
-  /* Temporary stack slot to use for SDmode copies.  This slot is
-     64-bits wide and is allocated early enough so that the offset
-     does not overflow the 16-bit load/store offset field.  */
-  rtx sdmode_stack_slot;
   /* Alternative internal arg pointer for -fsplit-stack.  */
   rtx split_stack_arg_pointer;
   bool split_stack_argp_used;
   /* Flag if r2 setup is needed with ELFv2 ABI.  */
   bool r2_setup_needed;
+  /* The number of components we use for separate shrink-wrapping.  */
+  int n_components;
   /* The components already handled by separate shrink-wrapping, which should
      not be considered by the prologue and epilogue.  */
   bool gpr_is_wrapped_separately[32];
+  bool fpr_is_wrapped_separately[32];
   bool lr_is_wrapped_separately;
+  bool toc_is_wrapped_separately;
 } machine_function;
 
 /* Support targetm.vectorize.builtin_mask_for_load.  */
@@ -181,9 +199,21 @@
 
 /* Specify the machine mode that pointers have.  After generation of rtl, the
    compiler makes no further distinction between pointers and any other objects
-   of this machine mode.  The type is unsigned since not all things that
-   include rs6000.h also include machmode.h.  */
-unsigned rs6000_pmode;
+   of this machine mode.  */
+scalar_int_mode rs6000_pmode;
+
+#if TARGET_ELF
+/* Note whether IEEE 128-bit floating point was passed or returned, either as
+   the __float128/_Float128 explicit type, or when long double is IEEE 128-bit
+   floating point.  We changed the default C++ mangling for these types and we
+   may want to generate a weak alias of the old mangling (U10__float128) to the
+   new mangling (u9__ieee128).  */
+static bool rs6000_passes_ieee128;
+#endif
+
+/* Generate the manged name (i.e. U10__float128) used in GCC 8.1, and not the
+   name used in current releases (i.e. u9__ieee128).  */
+static bool ieee128_mangling_gcc_8_1;
 
 /* Width in bits of a pointer.  */
 unsigned rs6000_pointer_size;
@@ -206,7 +236,8 @@
 #endif
 
 /* Value is TRUE if register/mode pair is acceptable.  */
-bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
+static bool rs6000_hard_regno_mode_ok_p
+  [NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
 
 /* Maximum number of registers needed for a given register class and mode.  */
 unsigned char rs6000_class_max_nregs[NUM_MACHINE_MODES][LIM_REG_CLASSES];
@@ -385,6 +416,34 @@
   { "scv",             PPC_FEATURE2_SCV,               1 }
 };
 
+/* On PowerPC, we have a limited number of target clones that we care about
+   which means we can use an array to hold the options, rather than having more
+   elaborate data structures to identify each possible variation.  Order the
+   clones from the default to the highest ISA.  */
+enum {
+  CLONE_DEFAULT                = 0,            /* default clone.  */
+  CLONE_ISA_2_05,                      /* ISA 2.05 (power6).  */
+  CLONE_ISA_2_06,                      /* ISA 2.06 (power7).  */
+  CLONE_ISA_2_07,                      /* ISA 2.07 (power8).  */
+  CLONE_ISA_3_00,                      /* ISA 3.00 (power9).  */
+  CLONE_MAX
+};
+
+/* Map compiler ISA bits into HWCAP names.  */
+struct clone_map {
+  HOST_WIDE_INT isa_mask;      /* rs6000_isa mask */
+  const char *name;            /* name to use in __builtin_cpu_supports.  */
+};
+
+static const struct clone_map rs6000_clone_map[CLONE_MAX] = {
+  { 0,                         "" },           /* Default options.  */
+  { OPTION_MASK_CMPB,          "arch_2_05" },  /* ISA 2.05 (power6).  */
+  { OPTION_MASK_POPCNTD,       "arch_2_06" },  /* ISA 2.06 (power7).  */
+  { OPTION_MASK_P8_VECTOR,     "arch_2_07" },  /* ISA 2.07 (power8).  */
+  { OPTION_MASK_P9_VECTOR,     "arch_3_00" },  /* ISA 3.00 (power9).  */
+};
+
+
 /* Newer LIBCs explicitly export this symbol to declare that they provide
    the AT_PLATFORM and AT_HWCAP/AT_HWCAP2 values in the TCB.  We emit a
    reference to this symbol whenever we expand a CPU builtin, so that
@@ -412,9 +471,7 @@
   ALTIVEC_REG_TYPE,
   FPR_REG_TYPE,
   SPR_REG_TYPE,
-  CR_REG_TYPE,
-  SPE_ACC_TYPE,
-  SPEFSCR_REG_TYPE
+  CR_REG_TYPE
 };
 
 /* Map register class to register type.  */
@@ -614,31 +671,10 @@
 }
 
 
-/* Target cpu costs.  */
-
-struct processor_costs {
-  const int mulsi;       /* cost of SImode multiplication.  */
-  const int mulsi_const;  /* cost of SImode multiplication by constant.  */
-  const int mulsi_const9; /* cost of SImode mult by short constant.  */
-  const int muldi;       /* cost of DImode multiplication.  */
-  const int divsi;       /* cost of SImode division.  */
-  const int divdi;       /* cost of DImode division.  */
-  const int fp;                  /* cost of simple SFmode and DFmode insns.  */
-  const int dmul;        /* cost of DFmode multiplication (and fmadd).  */
-  const int sdiv;        /* cost of SFmode division (fdivs).  */
-  const int ddiv;        /* cost of DFmode division (fdiv).  */
-  const int cache_line_size;    /* cache line size in bytes. */
-  const int l1_cache_size;     /* size of l1 cache, in kilobytes.  */
-  const int l2_cache_size;     /* size of l2 cache, in kilobytes.  */
-  const int simultaneous_prefetches; /* number of parallel prefetch
-                                       operations.  */
-  const int sfdf_convert;      /* cost of SF->DF conversion.  */
-};
+/* Processor costs (relative to an add) */
 
 const struct processor_costs *rs6000_cost;
 
-/* Processor costs (relative to an add) */
-
 /* Instruction size costs on 32bit processors.  */
 static const
 struct processor_costs size32_cost = {
@@ -1248,11 +1284,9 @@
 #undef RS6000_BUILTIN_3
 #undef RS6000_BUILTIN_A
 #undef RS6000_BUILTIN_D
-#undef RS6000_BUILTIN_E
 #undef RS6000_BUILTIN_H
 #undef RS6000_BUILTIN_P
 #undef RS6000_BUILTIN_Q
-#undef RS6000_BUILTIN_S
 #undef RS6000_BUILTIN_X
 
 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
@@ -1273,9 +1307,6 @@
 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)  \
   { NAME, ICODE, MASK, ATTR },
 
-#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)  \
-  { NAME, ICODE, MASK, ATTR },
-
 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)  \
   { NAME, ICODE, MASK, ATTR },
 
@@ -1285,9 +1316,6 @@
 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)  \
   { NAME, ICODE, MASK, ATTR },
 
-#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)  \
-  { NAME, ICODE, MASK, ATTR },
-
 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)  \
   { NAME, ICODE, MASK, ATTR },
 
@@ -1309,11 +1337,9 @@
 #undef RS6000_BUILTIN_3
 #undef RS6000_BUILTIN_A
 #undef RS6000_BUILTIN_D
-#undef RS6000_BUILTIN_E
 #undef RS6000_BUILTIN_H
 #undef RS6000_BUILTIN_P
 #undef RS6000_BUILTIN_Q
-#undef RS6000_BUILTIN_S
 #undef RS6000_BUILTIN_X
 
 /* Support for -mveclibabi=<xxx> to control which vector library to use.  */
@@ -1321,7 +1347,6 @@
 
 



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