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[src/trunk]: src/sys/arch/arm/imx Add i.MX SPI device type.
details: https://anonhg.NetBSD.org/src/rev/e44594dd0332
branches: trunk
changeset: 459828:e44594dd0332
user: hkenken <hkenken%NetBSD.org@localhost>
date: Fri Sep 27 02:59:21 2019 +0000
description:
Add i.MX SPI device type.
IMX31_CSPI
IMX35_CSPI
IMX51_ECSPI
diffstat:
sys/arch/arm/imx/fdt/imx6_spi.c | 21 +++++++++++++++++----
sys/arch/arm/imx/imx51_spi.c | 8 ++++++--
sys/arch/arm/imx/imxcspireg.h | 39 +++++++++++++++------------------------
sys/arch/arm/imx/imxecspireg.h | 4 ++--
sys/arch/arm/imx/imxspi.c | 34 ++++++++++++++++++----------------
sys/arch/arm/imx/imxspivar.h | 9 ++++++++-
6 files changed, 66 insertions(+), 49 deletions(-)
diffs (274 lines):
diff -r f08a08fcb973 -r e44594dd0332 sys/arch/arm/imx/fdt/imx6_spi.c
--- a/sys/arch/arm/imx/fdt/imx6_spi.c Fri Sep 27 02:54:57 2019 +0000
+++ b/sys/arch/arm/imx/fdt/imx6_spi.c Fri Sep 27 02:59:21 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: imx6_spi.c,v 1.1 2019/08/19 11:41:36 hkenken Exp $ */
+/* $NetBSD: imx6_spi.c,v 1.2 2019/09/27 02:59:21 hkenken Exp $ */
/*-
* Copyright (c) 2019 Genetec Corporation. All rights reserved.
* Written by Hashimoto Kenichi for Genetec Corporation.
@@ -25,7 +25,7 @@
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: imx6_spi.c,v 1.1 2019/08/19 11:41:36 hkenken Exp $");
+__KERNEL_RCSID(0, "$NetBSD: imx6_spi.c,v 1.2 2019/09/27 02:59:21 hkenken Exp $");
#include "opt_imxspi.h"
@@ -48,8 +48,18 @@
struct fdtbus_gpio_pin **sc_pin_cs;
};
+struct imx_spi_config {
+ bool enhanced;
+ enum imxspi_type type;
+};
+
+static const struct imx_spi_config imx6q_spi_config = {
+ .enhanced = true,
+ .type = IMX51_ECSPI,
+};
+
static const struct of_compat_data compat_data[] = {
- { "fsl,imx6q-ecspi", true },
+ { "fsl,imx6q-ecspi", (uintptr_t)&imx6q_spi_config },
{ NULL }
};
@@ -122,7 +132,10 @@
sc->sc_phandle = phandle;
sc->sc_iot = faa->faa_bst;
- sc->sc_enhanced = of_search_compatible(phandle, compat_data)->data;
+
+ struct imx_spi_config *config = (void *)of_search_compatible(phandle, compat_data)->data;
+ sc->sc_enhanced = config->enhanced;
+ sc->sc_type = config->type;
sc->sc_nslaves = nslaves;
sc->sc_freq = clk_get_rate(ifsc->sc_clk);
diff -r f08a08fcb973 -r e44594dd0332 sys/arch/arm/imx/imx51_spi.c
--- a/sys/arch/arm/imx/imx51_spi.c Fri Sep 27 02:54:57 2019 +0000
+++ b/sys/arch/arm/imx/imx51_spi.c Fri Sep 27 02:59:21 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: imx51_spi.c,v 1.2 2019/08/19 11:41:36 hkenken Exp $ */
+/* $NetBSD: imx51_spi.c,v 1.3 2019/09/27 02:59:21 hkenken Exp $ */
/*-
* Copyright (c) 2014 Genetec Corporation. All rights reserved.
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: imx51_spi.c,v 1.2 2019/08/19 11:41:36 hkenken Exp $");
+__KERNEL_RCSID(0, "$NetBSD: imx51_spi.c,v 1.3 2019/09/27 02:59:21 hkenken Exp $");
#include "locators.h"
#include "opt_imx.h"
@@ -95,6 +95,10 @@
sc->sc_iot = aa->aa_iot;
sc->sc_enhanced = cf_flags;
+ if (sc->sc_enhanced)
+ sc->sc_type = IMX51_ECSPI;
+ else
+ sc->sc_type = IMX35_CSPI;
sc->sc_nslaves = IMXSPINSLAVES;
sc->sc_freq = imx51_get_clock(IMX51CLK_CSPI_CLK_ROOT);
diff -r f08a08fcb973 -r e44594dd0332 sys/arch/arm/imx/imxcspireg.h
--- a/sys/arch/arm/imx/imxcspireg.h Fri Sep 27 02:54:57 2019 +0000
+++ b/sys/arch/arm/imx/imxcspireg.h Fri Sep 27 02:59:21 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: imxcspireg.h,v 1.1 2014/03/22 09:28:08 hkenken Exp $ */
+/* $NetBSD: imxcspireg.h,v 1.2 2019/09/27 02:59:21 hkenken Exp $ */
/*
* Copyright (c) 2014 Genetec Corporation. All rights reserved.
@@ -32,15 +32,12 @@
#define CSPI_RXDATA 0x00
#define CSPI_TXDATA 0x04
#define CSPI_CONREG 0x08
-#ifdef IMX51
-#define CSPI_CON_CS __BITS(13, 12)
-#define CSPI_CON_DRCTL __BITS( 9, 8)
-#define CSPI_CON_BITCOUNT __BITS(31, 20)
-#else
-#define CSPI_CON_CS __BITS(25, 24)
-#define CSPI_CON_DRCTL __BITS(21, 20)
-#define CSPI_CON_BITCOUNT __BITS(12, 8)
-#endif
+#define CSPI_IMX31_CON_CS __BITS(25, 24)
+#define CSPI_IMX31_CON_DRCTL __BITS(21, 20)
+#define CSPI_IMX31_CON_BITCOUNT __BITS(12, 8)
+#define CSPI_IMX35_CON_CS __BITS(13, 12)
+#define CSPI_IMX35_CON_DRCTL __BITS( 9, 8)
+#define CSPI_IMX35_CON_BITCOUNT __BITS(31, 20)
#define CSPI_CON_DIV __BITS(18, 16)
#define CSPI_CON_SSPOL __BIT(7) /* SPI SS Polarity Select */
#define CSPI_CON_SSCTL __BIT(6) /* In master mode, this bit
@@ -55,12 +52,9 @@
#define CSPI_CON_ENABLE __BIT(0) /* EN */
#define CSPI_INTREG 0x0c
#define CSPI_INTR_ALL_EN 0x000001ff /* All Intarruption Enabled */
-#ifdef IMX51
-#define CSPI_INTR_TC_EN __BIT(7) /* TX Complete */
-#else
-#define CSPI_INTR_TC_EN __BIT(8) /* TX Complete */
-#define CSPI_INTR_BO_EN __BIT(7) /* Bit Counter Overflow */
-#endif
+#define CSPI_IMX31_INTR_TC_EN __BIT(8) /* TX Complete */
+#define CSPI_IMX31_INTR_BO_EN __BIT(7) /* Bit Counter Overflow */
+#define CSPI_IMX35_INTR_TC_EN __BIT(7) /* TX Complete */
#define CSPI_INTR_RO_EN __BIT(6) /* RXFIFO Overflow */
#define CSPI_INTR_RF_EN __BIT(5) /* RXFIFO Full */
#define CSPI_INTR_RH_EN __BIT(4) /* RXFIFO Half Full */
@@ -70,14 +64,11 @@
#define CSPI_INTR_TE_EN __BIT(0) /* TXFIFO Empty */
#define CSPI_DMAREG 0x10
#define CSPI_STATREG 0x14
-#ifdef IMX51
-#define CSPI_STAT_CLR_TC __BIT(7) /* Clear TC of status register */
-#define CSPI_STAT_CLR CSPI_STAT_CLR_TC
-#else
-#define CSPI_STAT_CLR_TC __BIT(8) /* Clear TC of status register */
-#define CSPI_STAT_CLR_BO __BIT(7) /* Clear BO of status register */
-#define CSPI_STAT_CLR (CSPI_STAT_CLR_TC | CSPI_STAT_CLR_BO)
-#endif
+#define CSPI_IMX31_STAT_CLR_TC __BIT(8) /* Clear TC of status register */
+#define CSPI_IMX31_STAT_CLR_BO __BIT(7) /* Clear BO of status register */
+#define CSPI_IMX31_STAT_CLR (CSPI_IMX31_STAT_CLR_TC | CSPI_IMX31_STAT_CLR_BO)
+#define CSPI_IMX35_STAT_CLR_TC __BIT(7) /* Clear TC of status register */
+#define CSPI_IMX35_STAT_CLR CSPI_IMX35_STAT_CLR_TC
#define CSPI_STAT_RO __BIT(6) /* RXFIFO Overflow */
#define CSPI_STAT_RF __BIT(5) /* RXFIFO Full */
#define CSPI_STAT_RH __BIT(4) /* RXFIFO Half Full */
diff -r f08a08fcb973 -r e44594dd0332 sys/arch/arm/imx/imxecspireg.h
--- a/sys/arch/arm/imx/imxecspireg.h Fri Sep 27 02:54:57 2019 +0000
+++ b/sys/arch/arm/imx/imxecspireg.h Fri Sep 27 02:59:21 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: imxecspireg.h,v 1.1 2014/03/22 09:28:08 hkenken Exp $ */
+/* $NetBSD: imxecspireg.h,v 1.2 2019/09/27 02:59:21 hkenken Exp $ */
/*
* Copyright (c) 2012 Genetec Corporation. All rights reserved.
@@ -32,7 +32,7 @@
#define ECSPI_RXDATA 0x00
#define ECSPI_TXDATA 0x04
#define ECSPI_CONREG 0x08
-#define ECSPI_CON_BITCOUNT __BITS(31, 20)
+#define ECSPI_CON_BITCOUNT __BITS(31,20)
#define ECSPI_CON_CS __BITS(19,18)
#define ECSPI_CON_DRCTL __BITS(17,16)
#define ECSPI_CON_PREDIV __BITS(15,12) /* PRE DIVIDER */
diff -r f08a08fcb973 -r e44594dd0332 sys/arch/arm/imx/imxspi.c
--- a/sys/arch/arm/imx/imxspi.c Fri Sep 27 02:54:57 2019 +0000
+++ b/sys/arch/arm/imx/imxspi.c Fri Sep 27 02:59:21 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: imxspi.c,v 1.5 2019/08/19 11:41:36 hkenken Exp $ */
+/* $NetBSD: imxspi.c,v 1.6 2019/09/27 02:59:21 hkenken Exp $ */
/*-
* Copyright (c) 2014 Genetec Corporation. All rights reserved.
@@ -32,9 +32,8 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: imxspi.c,v 1.5 2019/08/19 11:41:36 hkenken Exp $");
+__KERNEL_RCSID(0, "$NetBSD: imxspi.c,v 1.6 2019/09/27 02:59:21 hkenken Exp $");
-#include "opt_imx.h"
#include "opt_imxspi.h"
#include "opt_fdt.h"
@@ -68,8 +67,13 @@
void imxspi_recv(struct imxspi_softc *);
void imxspi_sched(struct imxspi_softc *);
-#define IMXSPI(x) \
- ((sc->sc_enhanced) ? __CONCAT(ECSPI_, x) : __CONCAT(CSPI_, x))
+#define IMXCSPI_TYPE(type, x) \
+ ((sc->sc_type == IMX31_CSPI) ? __CONCAT(CSPI_IMX31_, x) : \
+ (sc->sc_type == IMX35_CSPI) ? __CONCAT(CSPI_IMX35_, x) : 0)
+#define IMXCSPI(x) __CONCAT(CSPI_, x)
+#define IMXESPI(x) __CONCAT(ECSPI_, x)
+#define IMXSPI(x) ((sc->sc_enhanced) ? IMXESPI(x) : IMXCSPI(x))
+#define IMXSPI_TYPE(x) ((sc->sc_enhanced) ? IMXESPI(x) : IMXCSPI_TYPE(sc->sc_type, x))
#define READ_REG(sc, x) \
bus_space_read_4(sc->sc_iot, sc->sc_ioh, IMXSPI(x))
#define WRITE_REG(sc, x, v) \
@@ -123,13 +127,13 @@
/* configure SPI */
/* Setup Control Register */
- WRITE_REG(sc, CONREG, __SHIFTIN(0, IMXSPI(CON_DRCTL)) |
- __SHIFTIN(8 - 1, IMXSPI(CON_BITCOUNT)) |
+ WRITE_REG(sc, CONREG,
+ __SHIFTIN(0, IMXSPI_TYPE(CON_DRCTL)) |
+ __SHIFTIN(8 - 1, IMXSPI_TYPE(CON_BITCOUNT)) |
__SHIFTIN(0xf, IMXSPI(CON_MODE)) | IMXSPI(CON_ENABLE));
-
/* TC and RR interruption */
- WRITE_REG(sc, INTREG, (IMXSPI(INTR_TC_EN) | IMXSPI(INTR_RR_EN)));
- WRITE_REG(sc, STATREG, IMXSPI(STAT_CLR));
+ WRITE_REG(sc, INTREG, (IMXSPI_TYPE(INTR_TC_EN) | IMXSPI(INTR_RR_EN)));
+ WRITE_REG(sc, STATREG, IMXSPI_TYPE(STAT_CLR));
WRITE_REG(sc, PERIODREG, 0x0);
@@ -332,8 +336,8 @@
/* chip slect */
chipselect = READ_REG(sc, CONREG);
- chipselect &= ~IMXSPI(CON_CS);
- chipselect |= __SHIFTIN(st->st_slave, IMXSPI(CON_CS));
+ chipselect &= ~IMXSPI_TYPE(CON_CS);
+ chipselect |= __SHIFTIN(st->st_slave, IMXSPI_TYPE(CON_CS));
WRITE_REG(sc, CONREG, chipselect);
delay(1);
@@ -398,11 +402,9 @@
imxspi_done(sc, err);
}
- /* Transfer Conplete? */
- if (sr & IMXSPI(INTR_TC_EN)) {
- /* complete TX */
+ /* Transfer Complete? */
+ if (sr & IMXSPI_TYPE(INTR_TC_EN))
imxspi_send(sc);
- }
/* status register clear */
WRITE_REG(sc, STATREG, sr);
diff -r f08a08fcb973 -r e44594dd0332 sys/arch/arm/imx/imxspivar.h
--- a/sys/arch/arm/imx/imxspivar.h Fri Sep 27 02:54:57 2019 +0000
+++ b/sys/arch/arm/imx/imxspivar.h Fri Sep 27 02:59:21 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: imxspivar.h,v 1.2 2019/08/19 11:41:36 hkenken Exp $ */
+/* $NetBSD: imxspivar.h,v 1.3 2019/09/27 02:59:21 hkenken Exp $ */
/*
* Copyright (c) 2014 Genetec Corporation. All rights reserved.
@@ -38,6 +38,12 @@
int (*spi_cs_disable)(void *, int);
} *spi_chipset_tag_t;
+enum imxspi_type {
+ IMX31_CSPI,
+ IMX35_CSPI,
+ IMX51_ECSPI,
+};
+
struct imxspi_softc {
device_t sc_dev;
int sc_phandle;
@@ -57,6 +63,7 @@
int sc_nslaves;
int sc_enhanced;
+ enum imxspi_type sc_type;
};
int imxspi_attach_common(device_t);
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