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[src/netbsd-9]: src/sys/dev/pci Pull up following revision(s) (requested by m...
details: https://anonhg.NetBSD.org/src/rev/ef9382eae109
branches: netbsd-9
changeset: 458401:ef9382eae109
user: martin <martin%NetBSD.org@localhost>
date: Thu Sep 26 18:52:57 2019 +0000
description:
Pull up following revision(s) (requested by msaitoh in ticket #243):
sys/dev/pci/pci_subr.c: revision 1.216
sys/dev/pci/pci_subr.c: revision 1.217
Whitespace fixes. No functional change.
-
Print some DPC register values not with %04x but with %08x because those
are 32bit.
diffstat:
sys/dev/pci/pci_subr.c | 73 ++++++++++++++++++++++++-------------------------
1 files changed, 36 insertions(+), 37 deletions(-)
diffs (260 lines):
diff -r 278e056b7a01 -r ef9382eae109 sys/dev/pci/pci_subr.c
--- a/sys/dev/pci/pci_subr.c Thu Sep 26 18:50:18 2019 +0000
+++ b/sys/dev/pci/pci_subr.c Thu Sep 26 18:52:57 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pci_subr.c,v 1.215 2019/07/18 07:49:26 msaitoh Exp $ */
+/* $NetBSD: pci_subr.c,v 1.215.2.1 2019/09/26 18:52:57 martin Exp $ */
/*
* Copyright (c) 1997 Zubin D. Dittia. All rights reserved.
@@ -40,7 +40,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.215 2019/07/18 07:49:26 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.215.2.1 2019/09/26 18:52:57 martin Exp $");
#ifdef _KERNEL_OPT
#include "opt_pci.h"
@@ -209,7 +209,7 @@
/* PCI bridge programming interface */
static const struct pci_class pci_interface_pcibridge[] = {
- { "", PCI_INTERFACE_BRIDGE_PCI_PCI, NULL, },
+ { "", PCI_INTERFACE_BRIDGE_PCI_PCI, NULL, },
{ "subtractive decode", PCI_INTERFACE_BRIDGE_PCI_SUBDEC, NULL, },
{ NULL, 0, NULL, },
};
@@ -223,8 +223,8 @@
/* Advanced Switching programming interface */
static const struct pci_class pci_interface_advsw[] = {
- { "custom interface", PCI_INTERFACE_ADVSW_CUSTOM, NULL, },
- { "ASI-SIG", PCI_INTERFACE_ADVSW_ASISIG, NULL, },
+ { "custom interface", PCI_INTERFACE_ADVSW_CUSTOM, NULL, },
+ { "ASI-SIG", PCI_INTERFACE_ADVSW_ASISIG, NULL, },
{ NULL, 0, NULL, },
};
@@ -304,7 +304,7 @@
/*
* Class 0x08.
* Base system peripheral.
- */
+ */
/* PIC programming interface */
static const struct pci_class pci_interface_pic[] = {
@@ -429,10 +429,10 @@
/* IPMI programming interface */
static const struct pci_class pci_interface_ipmi[] = {
- { "SMIC", PCI_INTERFACE_IPMI_SMIC, NULL,},
- { "keyboard", PCI_INTERFACE_IPMI_KBD, NULL,},
- { "block transfer", PCI_INTERFACE_IPMI_BLOCKXFER, NULL,},
- { NULL, 0, NULL,},
+ { "SMIC", PCI_INTERFACE_IPMI_SMIC, NULL, },
+ { "keyboard", PCI_INTERFACE_IPMI_KBD, NULL, },
+ { "block transfer", PCI_INTERFACE_IPMI_BLOCKXFER, NULL, },
+ { NULL, 0, NULL, },
};
/* Subclasses */
@@ -478,8 +478,8 @@
/* Intelligent IO programming interface */
static const struct pci_class pci_interface_i2o[] = {
- { "FIFO at offset 0x40", PCI_INTERFACE_I2O_FIFOAT40, NULL,},
- { NULL, 0, NULL,},
+ { "FIFO at offset 0x40", PCI_INTERFACE_I2O_FIFOAT40, NULL, },
+ { NULL, 0, NULL, },
};
/* Subclasses */
@@ -494,9 +494,9 @@
* Satellite communication controller.
*/
static const struct pci_class pci_subclass_satcom[] = {
- { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, },
- { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, },
- { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, },
+ { "TV", PCI_SUBCLASS_SATCOM_TV, NULL, },
+ { "audio", PCI_SUBCLASS_SATCOM_AUDIO, NULL, },
+ { "voice", PCI_SUBCLASS_SATCOM_VOICE, NULL, },
{ "data", PCI_SUBCLASS_SATCOM_DATA, NULL, },
{ "miscellaneous", PCI_SUBCLASS_SATCOM_MISC, NULL, },
{ NULL, 0, NULL, },
@@ -507,9 +507,9 @@
* Encryption/Decryption controller.
*/
static const struct pci_class pci_subclass_crypto[] = {
- { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, },
+ { "network/computing", PCI_SUBCLASS_CRYPTO_NETCOMP, NULL, },
{ "entertainment", PCI_SUBCLASS_CRYPTO_ENTERTAINMENT, NULL,},
- { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, },
+ { "miscellaneous", PCI_SUBCLASS_CRYPTO_MISC, NULL, },
{ NULL, 0, NULL, },
};
@@ -585,7 +585,7 @@
* a positive value if the dest buffer would have overflowed.
*/
-static int __printflike(3,4)
+static int __printflike(3, 4)
snappendf(char **dest, size_t *len, const char * restrict fmt, ...)
{
va_list ap;
@@ -609,7 +609,7 @@
/* Update dest & len to point at trailing NUL */
*dest += count;
*len -= count;
-
+
return 0;
}
@@ -1285,7 +1285,7 @@
printf("PCI-X 266 (Mode 2)\n");
else
printf("PCI-X 533 (Mode 2)\n");
-
+
printf(" Error protection: %s\n", (num <= 3) ? "parity" : "ECC");
switch (num & 0x03) {
default:
@@ -1564,7 +1564,7 @@
onoff("IOMMU Miscellaneous Information Register 1", reg,
PCI_SECURE_CAP_EXT);
havemisc1 = reg & PCI_SECURE_CAP_EXT;
-
+
reg = regs[o2i(capoff + PCI_SECURE_IOMMU_BAL)];
printf(" Base Address Low Register: 0x%08x\n", reg);
onoff("Enable", reg, PCI_SECURE_IOMMU_BAL_EN);
@@ -1573,7 +1573,7 @@
printf(" Base Address: 0x%016" PRIx64 "\n",
((uint64_t)reg2 << 32)
| (reg & (PCI_SECURE_IOMMU_BAL_H | PCI_SECURE_IOMMU_BAL_L)));
-
+
reg = regs[o2i(capoff + PCI_SECURE_IOMMU_RANGE)];
printf(" IOMMU Range Register: 0x%08x\n", reg);
printf(" HyperTransport UnitID: 0x%02x\n",
@@ -1607,7 +1607,7 @@
if (!havemisc1)
return;
-
+
reg = regs[o2i(capoff + PCI_SECURE_IOMMU_MISC1)];
printf(" Miscellaneous Information Register 1: 0x%08x\n", reg);
printf(" MSI Message number (GA): 0x%02x\n",
@@ -1985,7 +1985,7 @@
if (check_slot == true) {
pcireg_t slcap;
-
+
/* Slot Capability Register */
slcap = reg = regs[o2i(capoff + PCIE_SLCAP)];
printf(" Slot Capability Register: 0x%08x\n", reg);
@@ -2146,7 +2146,6 @@
default:
printf("(reserved value)\n");
break;
-
}
printf(" LN System CLS: ");
switch (__SHIFTOUT(reg, PCIE_DCAP2_LNSYSCLS)) {
@@ -2340,7 +2339,7 @@
reg = regs[o2i(capoff + PCI_MSIX_CTL)];
printf(" Message Control register: 0x%04x\n",
(reg >> 16) & 0xff);
- printf(" Table Size: %d\n",PCI_MSIX_CTL_TBLSIZE(reg));
+ printf(" Table Size: %d\n", PCI_MSIX_CTL_TBLSIZE(reg));
onoff("Function Mask", reg, PCI_MSIX_CTL_FUNCMASK);
onoff("MSI-X Enable", reg, PCI_MSIX_CTL_ENABLE);
reg = regs[o2i(capoff + PCI_MSIX_TBLOFFSET)];
@@ -2517,14 +2516,14 @@
printf("Reserved\n");
break;
}
-
+
printf(" Primary Properties: ");
pci_conf_print_ea_cap_prop(__SHIFTOUT(reg, PCI_EA_PP));
printf(" Secondary Properties: ");
pci_conf_print_ea_cap_prop(__SHIFTOUT(reg, PCI_EA_SP));
onoff("Writable", reg, PCI_EA_W);
onoff("Enable for this entry", reg, PCI_EA_E);
-
+
if (entry_size == 0) {
entoff += 4;
continue;
@@ -2577,7 +2576,7 @@
{ PCI_CAP_AGP, "AGP", pci_conf_print_agp_cap },
{ PCI_CAP_VPD, "VPD", NULL },
{ PCI_CAP_SLOTID, "SlotID", NULL },
- { PCI_CAP_MSI, "MSI", pci_conf_print_msi_cap },
+ { PCI_CAP_MSI, "MSI", pci_conf_print_msi_cap },
{ PCI_CAP_CPCI_HOTSWAP, "CompactPCI Hot-swapping", NULL },
{ PCI_CAP_PCIX, "PCI-X", pci_conf_print_pcix_cap },
{ PCI_CAP_LDT, "HyperTransport", pci_conf_print_ht_cap },
@@ -2620,7 +2619,7 @@
default:
return 0;
}
-
+
for (off = PCI_CAPLIST_PTR(regs[o2i(capptr)]);
off != 0; off = PCI_CAPLIST_NEXT(rval)) {
rval = regs[o2i(off)];
@@ -3150,7 +3149,7 @@
reg = regs[o2i(extcapoff + PCI_RCLINK_DCL_LINKDESC(i))];
printf(" Link Entry %d:\n", i + 1);
printf(" Link Description Register: 0x%08x\n", reg);
- onoff(" Link Valid", reg,PCI_RCLINK_DCL_LINKDESC_LVALID);
+ onoff(" Link Valid", reg, PCI_RCLINK_DCL_LINKDESC_LVALID);
linktype = reg & PCI_RCLINK_DCL_LINKDESC_LTYPE;
onoff2(" Link Type", reg, PCI_RCLINK_DCL_LINKDESC_LTYPE,
"Configuration Space", "Memory-Mapped Space");
@@ -3558,7 +3557,7 @@
pcireg_t cap, ctl;
unsigned int bars, i, n;
char pbuf[MEM_PBUFSIZE];
-
+
printf("\n Resizable BAR\n");
/* Get Number of Resizable BARs */
@@ -3991,23 +3990,23 @@
*/
reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_STAT)];
- printf(" RP PIO Status Register: 0x%04x\n", reg);
+ printf(" RP PIO Status Register: 0x%08x\n", reg);
pci_conf_print_dpc_pio(reg);
reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_MASK)];
- printf(" RP PIO Mask Register: 0x%04x\n", reg);
+ printf(" RP PIO Mask Register: 0x%08x\n", reg);
pci_conf_print_dpc_pio(reg);
reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_SEVE)];
- printf(" RP PIO Severity Register: 0x%04x\n", reg);
+ printf(" RP PIO Severity Register: 0x%08x\n", reg);
pci_conf_print_dpc_pio(reg);
reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_SYSERR)];
- printf(" RP PIO SysError Register: 0x%04x\n", reg);
+ printf(" RP PIO SysError Register: 0x%08x\n", reg);
pci_conf_print_dpc_pio(reg);
reg = regs[o2i(extcapoff + PCI_DPC_RPPIO_EXCPT)];
- printf(" RP PIO Exception Register: 0x%04x\n", reg);
+ printf(" RP PIO Exception Register: 0x%08x\n", reg);
pci_conf_print_dpc_pio(reg);
printf(" RP PIO Header Log Register: start from 0x%03x\n",
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