[src/netbsd-9]: src/sys/arch/aarch64/aarch64 Pull up following revision(s) (r...

[martin <martin%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/28502e7d76ff
branches:  netbsd-9
changeset: 458364:28502e7d76ff
user:      martin <martin%NetBSD.org@localhost>
date:      Sun Sep 22 10:29:44 2019 +0000

description:
Pull up following revision(s) (requested by ryo in ticket #213):

        sys/arch/aarch64/aarch64/cpufunc_asm_armv8.S: revision 1.4

even if "no options MULTIPROCESSOR" requires isb after tlbi op. since it should be harmless, dsb is also added.
fixed a problem that rockpro64 doesn't boot without MULTIPROCESSOR.

diffstat:

 sys/arch/aarch64/aarch64/cpufunc_asm_armv8.S |  22 +++++++++-------------
 1 files changed, 9 insertions(+), 13 deletions(-)

diffs (50 lines):

diff -r c4b4b19a35a5 -r 28502e7d76ff sys/arch/aarch64/aarch64/cpufunc_asm_armv8.S
--- a/sys/arch/aarch64/aarch64/cpufunc_asm_armv8.S      Sun Sep 22 10:24:09 2019 +0000
+++ b/sys/arch/aarch64/aarch64/cpufunc_asm_armv8.S      Sun Sep 22 10:29:44 2019 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cpufunc_asm_armv8.S,v 1.3 2018/12/21 08:01:01 ryo Exp $        */
+/*     $NetBSD: cpufunc_asm_armv8.S,v 1.3.4.1 2019/09/22 10:29:44 martin Exp $ */
 
 /*-
  * Copyright (c) 2014 Robin Randhawa
@@ -243,16 +243,14 @@
        /* x8 = bit 63[ASID]48, 47[RES0]44, 43[VA(55:12)]0 */
        lsl     x8, x0, #48
        bfxil   x8, x1, #12, #44
+       dsb     ishst
 #ifdef MULTIPROCESSOR
-       /* need dsb and isb for inner shareable? */
-       dsb     ishst
        tlbi    vae1is, x8
+#else
+       tlbi    vae1, x8
+#endif
        dsb     ish
        isb
-#else
-       /* no need dsb and isb for single entry */
-       tlbi    vae1, x8
-#endif
        ret
 END(aarch64_tlbi_by_asid_va)
 
@@ -261,15 +259,13 @@
        /* x8 = bit 63[ASID]48, 47[RES0]44, 43[VA(55:12)]0 */
        lsl     x8, x0, #48
        bfxil   x8, x1, #12, #44
+       dsb     ishst
 #ifdef MULTIPROCESSOR
-       /* need dsb and isb for inner shareable? */
-       dsb     ishst
        tlbi    vale1is, x8
+#else
+       tlbi    vale1, x8
+#endif
        dsb     ish
        isb
-#else
-       /* no need dsb and isb for single entry */
-       tlbi    vale1, x8
-#endif
        ret
 END(aarch64_tlbi_by_asid_va_ll)