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[src/trunk]: src/sys/dev/pci Improve SB800 and newer chipsets support:
details: https://anonhg.NetBSD.org/src/rev/b7fd3fdf8cb5
branches: trunk
changeset: 457698:b7fd3fdf8cb5
user: msaitoh <msaitoh%NetBSD.org@localhost>
date: Sat Jul 13 09:24:17 2019 +0000
description:
Improve SB800 and newer chipsets support:
- Add newer chipset (e.g. X370/X399 and newer) support that the PCI device id
is 0x790b. The register definitions are mainly taken from FreeBSD.
- Rename PIIXPM_INDIRECTIO_* to SB800_INDIRECTIO_* because those are only
for SB800 and newer chipsets.
- SB800 also support 4 ports.
- SB800's interrupt configuration bit is different from others.
Use SB800_SMB_HOSTC's bit 0.
- Do not bus_space_map devices which are at address 0 (it's uninitialized)
in piixpm_attach().
- Add the port number to the dmesg output.
- Avoid uninitiliazed use of ctl and corresponding warnings. From OpenBSD rev.
1.38
diffstat:
sys/dev/pci/piixpm.c | 180 +++++++++++++++++++++++++++++++----------------
sys/dev/pci/piixpmreg.h | 68 ++++++++++++++++-
2 files changed, 181 insertions(+), 67 deletions(-)
diffs (truncated from 459 to 300 lines):
diff -r bf478b3c9ce7 -r b7fd3fdf8cb5 sys/dev/pci/piixpm.c
--- a/sys/dev/pci/piixpm.c Fri Jul 12 23:32:45 2019 +0000
+++ b/sys/dev/pci/piixpm.c Sat Jul 13 09:24:17 2019 +0000
@@ -1,5 +1,5 @@
-/* $NetBSD: piixpm.c,v 1.53 2019/07/12 03:57:50 msaitoh Exp $ */
-/* $OpenBSD: piixpm.c,v 1.35 2011/04/09 04:33:40 deraadt Exp $ */
+/* $NetBSD: piixpm.c,v 1.54 2019/07/13 09:24:17 msaitoh Exp $ */
+/* $OpenBSD: piixpm.c,v 1.39 2013/10/01 20:06:02 sf Exp $ */
/*
* Copyright (c) 2005, 2006 Alexander Yurchenko <grange%openbsd.org@localhost>
@@ -22,7 +22,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: piixpm.c,v 1.53 2019/07/12 03:57:50 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: piixpm.c,v 1.54 2019/07/13 09:24:17 msaitoh Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -49,12 +49,27 @@
#define DPRINTF(x)
#endif
-#define PIIXPM_IS_CSB5(id) \
- (PCI_VENDOR((id)) == PCI_VENDOR_SERVERWORKS && \
- PCI_PRODUCT((id)) == PCI_PRODUCT_SERVERWORKS_CSB5)
+#define PIIXPM_IS_CSB5(sc) \
+ (PCI_VENDOR((sc)->sc_id) == PCI_VENDOR_SERVERWORKS && \
+ PCI_PRODUCT((sc)->sc_id) == PCI_PRODUCT_SERVERWORKS_CSB5)
#define PIIXPM_DELAY 200
#define PIIXPM_TIMEOUT 1
+#define PIIXPM_IS_SB800GRP(sc) \
+ ((PCI_VENDOR((sc)->sc_id) == PCI_VENDOR_ATI) && \
+ ((PCI_PRODUCT((sc)->sc_id) == PCI_PRODUCT_ATI_SB600_SMB) && \
+ ((sc)->sc_rev >= 0x40)))
+
+#define PIIXPM_IS_HUDSON(sc) \
+ ((PCI_VENDOR((sc)->sc_id) == PCI_VENDOR_AMD) && \
+ (PCI_PRODUCT((sc)->sc_id) == PCI_PRODUCT_AMD_HUDSON_SMB))
+
+#define PIIXPM_IS_KERNCZ(sc) \
+ ((PCI_VENDOR((sc)->sc_id) == PCI_VENDOR_AMD) && \
+ (PCI_PRODUCT((sc)->sc_id) == PCI_PRODUCT_AMD_KERNCZ_SMB))
+
+#define PIIXPM_IS_FCHGRP(sc) (PIIXPM_IS_HUDSON(sc) || PIIXPM_IS_KERNCZ(sc))
+
struct piixpm_smbus {
int sda;
struct piixpm_softc *softc;
@@ -75,6 +90,7 @@
pci_chipset_tag_t sc_pc;
pcitag_t sc_pcitag;
pcireg_t sc_id;
+ pcireg_t sc_rev;
int sc_numbusses;
device_t sc_i2c_device[4];
@@ -149,6 +165,7 @@
case PCI_VENDOR_AMD:
switch (PCI_PRODUCT(pa->pa_id)) {
case PCI_PRODUCT_AMD_HUDSON_SMB:
+ case PCI_PRODUCT_AMD_KERNCZ_SMB:
return 1;
}
break;
@@ -165,6 +182,7 @@
pcireg_t base, conf;
pcireg_t pmmisc;
pci_intr_handle_t ih;
+ bool usesmi = false;
const char *intrstr = NULL;
int i, flags;
char intrbuf[PCI_INTRSTR_LEN];
@@ -172,6 +190,7 @@
sc->sc_dev = self;
sc->sc_iot = pa->pa_iot;
sc->sc_id = pa->pa_id;
+ sc->sc_rev = PCI_REVISION(pa->pa_class);
sc->sc_pc = pa->pa_pc;
sc->sc_pcitag = pa->pa_tag;
sc->sc_numbusses = 1;
@@ -181,10 +200,6 @@
if (!pmf_device_register(self, piixpm_suspend, piixpm_resume))
aprint_error_dev(self, "couldn't establish power handler\n");
- /* Read configuration */
- conf = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_HOSTC);
- DPRINTF(("%s: conf 0x%x\n", device_xname(self), conf));
-
if ((PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) ||
(PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_INTEL_82371AB_PMC))
goto nopowermanagement;
@@ -208,48 +223,52 @@
* PIIX4 and PIIX4E have a bug in the timer latch, see Errata #20
* in the "Specification update" (document #297738).
*/
- acpipmtimer_attach(self, sc->sc_pm_iot, sc->sc_pm_ioh,
- PIIX_PM_PMTMR,
- (PCI_REVISION(pa->pa_class) < 3) ? ACPIPMT_BADLATCH : 0 );
+ acpipmtimer_attach(self, sc->sc_pm_iot, sc->sc_pm_ioh, PIIX_PM_PMTMR,
+ (PCI_REVISION(pa->pa_class) < 3) ? ACPIPMT_BADLATCH : 0);
nopowermanagement:
- /* SB800 rev 0x40+ and AMD HUDSON need special initialization */
- if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_AMD &&
- PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_AMD_HUDSON_SMB) {
- if (piixpm_sb800_init(sc) == 0) {
- goto attach_i2c;
- }
- aprint_normal_dev(self, "SMBus initialization failed\n");
- return;
- }
- if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATI &&
- PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATI_SB600_SMB &&
- PCI_REVISION(pa->pa_class) >= 0x40) {
+ /* SB800 rev 0x40+, AMD HUDSON and newer need special initialization */
+ if (PIIXPM_IS_FCHGRP(sc) || PIIXPM_IS_SB800GRP(sc)) {
if (piixpm_sb800_init(sc) == 0) {
sc->sc_numbusses = 4;
- goto attach_i2c;
+
+ /* Read configuration */
+ conf = pci_conf_read(pa->pa_pc, pa->pa_tag,
+ SB800_SMB_HOSTC);
+ DPRINTF(("%s: conf 0x%08x\n", device_xname(self),
+ conf));
+
+ usesmi = conf & SB800_SMB_HOSTC_SMI;
+ goto setintr;
}
aprint_normal_dev(self, "SMBus initialization failed\n");
return;
}
+ /* Read configuration */
+ conf = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_HOSTC);
+ DPRINTF(("%s: conf 0x%08x\n", device_xname(self), conf));
+
if ((conf & PIIX_SMB_HOSTC_HSTEN) == 0) {
aprint_normal_dev(self, "SMBus disabled\n");
return;
}
+ usesmi = (conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_SMI;
/* Map I/O space */
base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_BASE) & 0xffff;
- if (bus_space_map(sc->sc_smb_iot, PCI_MAPREG_IO_ADDR(base),
+ if (base == 0 ||
+ bus_space_map(sc->sc_smb_iot, PCI_MAPREG_IO_ADDR(base),
PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) {
aprint_error_dev(self, "can't map smbus I/O space\n");
return;
}
+setintr:
sc->sc_poll = 1;
aprint_normal_dev(self, "");
- if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_SMI) {
+ if (usesmi) {
/* No PCI IRQ */
aprint_normal("interrupting at SMI, ");
} else {
@@ -274,7 +293,6 @@
aprint_normal("\n");
-attach_i2c:
for (i = 0; i < sc->sc_numbusses; i++)
sc->sc_i2c_device[i] = NULL;
@@ -284,6 +302,20 @@
}
static int
+piixpm_iicbus_print(void *aux, const char *pnp)
+{
+ struct i2cbus_attach_args *iba = aux;
+ struct i2c_controller *tag = iba->iba_tag;
+ struct piixpm_smbus *bus = tag->ic_cookie;
+ struct piixpm_softc *sc = bus->softc;
+
+ iicbus_print(aux, pnp);
+ if (sc->sc_numbusses != 0)
+ aprint_normal(" port %d", bus->sda);
+
+ return UNCONF;
+}
+static int
piixpm_rescan(device_t self, const char *ifattr, const int *flags)
{
struct piixpm_softc *sc = device_private(self);
@@ -308,7 +340,7 @@
iba.iba_type = I2C_TYPE_SMBUS;
iba.iba_tag = &sc->sc_i2c_tags[i];
sc->sc_i2c_device[i] = config_found_ia(self, ifattr, &iba,
- iicbus_print);
+ piixpm_iicbus_print);
}
return 0;
@@ -367,39 +399,53 @@
bus_space_tag_t iot = sc->sc_iot;
bus_space_handle_t ioh; /* indirect I/O handle */
uint16_t val, base_addr;
+ bool enabled;
/* Fetch SMB base address */
if (bus_space_map(iot,
- PIIXPM_INDIRECTIO_BASE, PIIXPM_INDIRECTIO_SIZE, 0, &ioh)) {
+ SB800_INDIRECTIO_BASE, SB800_INDIRECTIO_SIZE, 0, &ioh)) {
device_printf(sc->sc_dev, "couldn't map indirect I/O space\n");
return EBUSY;
}
- bus_space_write_1(iot, ioh, PIIXPM_INDIRECTIO_INDEX,
- SB800_PM_SMBUS0EN_LO);
- val = bus_space_read_1(iot, ioh, PIIXPM_INDIRECTIO_DATA);
- bus_space_write_1(iot, ioh, PIIXPM_INDIRECTIO_INDEX,
- SB800_PM_SMBUS0EN_HI);
- val |= bus_space_read_1(iot, ioh, PIIXPM_INDIRECTIO_DATA) << 8;
- sc->sc_sb800_ioh = ioh;
+ if (PIIXPM_IS_FCHGRP(sc)) {
+ bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX,
+ AMDFCH41_PM_DECODE_EN0);
+ val = bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA);
+ enabled = val & AMDFCH41_SMBUS_EN;
+ if (!enabled)
+ return ENOENT;
- if ((val & SB800_PM_SMBUS0EN_ENABLE) == 0)
- return ENOENT;
-
- base_addr = val & SB800_PM_SMBUS0EN_BADDR;
+ bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX,
+ AMDFCH41_PM_DECODE_EN1);
+ val = bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA) << 8;
+ base_addr = val;
+ } else {
+ bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX,
+ SB800_PM_SMBUS0EN_LO);
+ val = bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA);
+ enabled = val & SB800_PM_SMBUS0EN_ENABLE;
+ if (!enabled)
+ return ENOENT;
- aprint_debug_dev(sc->sc_dev, "SMBus @ 0x%04x\n", base_addr);
+ bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX,
+ SB800_PM_SMBUS0EN_HI);
+ val |= bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA) << 8;
+ base_addr = val & SB800_PM_SMBUS0EN_BADDR;
- bus_space_write_1(iot, ioh, PIIXPM_INDIRECTIO_INDEX,
- SB800_PM_SMBUS0SELEN);
- bus_space_write_1(iot, ioh, PIIXPM_INDIRECTIO_DATA, 1); /* SMBUS0SEL */
+ bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX,
+ SB800_PM_SMBUS0SELEN);
+ bus_space_write_1(iot, ioh, SB800_INDIRECTIO_DATA,
+ SB800_PM_SMBUS0EN_ENABLE);
+ }
+
+ sc->sc_sb800_ioh = ioh;
+ aprint_debug_dev(sc->sc_dev, "SMBus @ 0x%04x\n", base_addr);
if (bus_space_map(iot, PCI_MAPREG_IO_ADDR(base_addr),
PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) {
aprint_error_dev(sc->sc_dev, "can't map smbus I/O space\n");
return EBUSY;
}
- aprint_normal_dev(sc->sc_dev, "polling (SB800)\n");
- sc->sc_poll = 1;
return 0;
}
@@ -434,12 +480,16 @@
if (!cold)
mutex_enter(&sc->sc_i2c_mutex);
- if (smbus->sda > 0) /* SB800 */
- {
+ if (PIIXPM_IS_KERNCZ(sc)) {
+ bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh,
+ SB800_INDIRECTIO_INDEX, AMDFCH41_PM_PORT_INDEX);
bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh,
- PIIXPM_INDIRECTIO_INDEX, SB800_PM_SMBUS0SEL);
+ SB800_INDIRECTIO_DATA, smbus->sda << 3);
+ } else if (PIIXPM_IS_SB800GRP(sc) || PIIXPM_IS_HUDSON(sc)) {
bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh,
- PIIXPM_INDIRECTIO_DATA, smbus->sda << 1);
+ SB800_INDIRECTIO_INDEX, SB800_PM_SMBUS0SEL);
+ bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh,
+ SB800_INDIRECTIO_DATA, smbus->sda << 1);
}
return 0;
@@ -451,16 +501,20 @@
struct piixpm_smbus *smbus = cookie;
struct piixpm_softc *sc = smbus->softc;
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