[src/trunk]: src/sys/arch/x86/x86 Add support for EnhancedIBRS, a more perfor...

[maxv <maxv%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/ab6c4c5ff325
branches:  trunk
changeset: 456215:ab6c4c5ff325
user:      maxv <maxv%NetBSD.org@localhost>
date:      Sat Apr 27 10:40:17 2019 +0000

description:
Add support for EnhancedIBRS, a more performant mitigation for SpectreV2,
available on future CPUs (or maybe they already exist now...).

diffstat:

 sys/arch/x86/x86/spectre.c |  38 +++++++++++++++++++++++++++++---------
 1 files changed, 29 insertions(+), 9 deletions(-)

diffs (95 lines):

diff -r 79386f999036 -r ab6c4c5ff325 sys/arch/x86/x86/spectre.c
--- a/sys/arch/x86/x86/spectre.c        Sat Apr 27 09:06:18 2019 +0000
+++ b/sys/arch/x86/x86/spectre.c        Sat Apr 27 10:40:17 2019 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: spectre.c,v 1.25 2019/03/23 10:02:05 maxv Exp $        */
+/*     $NetBSD: spectre.c,v 1.26 2019/04/27 10:40:17 maxv Exp $        */
 
 /*
  * Copyright (c) 2018 NetBSD Foundation, Inc.
@@ -34,7 +34,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: spectre.c,v 1.25 2019/03/23 10:02:05 maxv Exp $");
+__KERNEL_RCSID(0, "$NetBSD: spectre.c,v 1.26 2019/04/27 10:40:17 maxv Exp $");
 
 #include "opt_spectre.h"
 
@@ -54,7 +54,8 @@
 enum v2_mitigation {
        V2_MITIGATION_NONE,
        V2_MITIGATION_AMD_DIS_IND,
-       V2_MITIGATION_INTEL_IBRS
+       V2_MITIGATION_INTEL_IBRS,
+       V2_MITIGATION_INTEL_ENHANCED_IBRS
 };
 
 enum v4_mitigation {
@@ -102,6 +103,9 @@
                case V2_MITIGATION_INTEL_IBRS:
                        strlcat(name, "[Intel IBRS]", sizeof(name));
                        break;
+               case V2_MITIGATION_INTEL_ENHANCED_IBRS:
+                       strlcat(name, "[Intel Enhanced IBRS]", sizeof(name));
+                       break;
                default:
                        panic("%s: impossible", __func__);
                }
@@ -116,20 +120,26 @@
 {
        struct cpu_info *ci = curcpu();
        u_int descs[4];
+       uint64_t msr;
 
        if (cpu_vendor == CPUVENDOR_INTEL) {
                if (cpuid_level >= 7) {
                        x86_cpuid(7, descs);
+
+                       if (descs[3] & CPUID_SEF_ARCH_CAP) {
+                               msr = rdmsr(MSR_IA32_ARCH_CAPABILITIES);
+                               if (msr & IA32_ARCH_IBRS_ALL) {
+                                       v2_mitigation_method =
+                                           V2_MITIGATION_INTEL_ENHANCED_IBRS;
+                                       return;
+                               }
+                       }
+#ifdef __x86_64__
                        if (descs[3] & CPUID_SEF_IBRS) {
-                               /* descs[3] = %edx */
-#ifdef __x86_64__
                                v2_mitigation_method = V2_MITIGATION_INTEL_IBRS;
-#else
-                               /* IBRS not supported on i386. */
-                               v2_mitigation_method = V2_MITIGATION_NONE;
-#endif
                                return;
                        }
+#endif
                }
                v2_mitigation_method = V2_MITIGATION_NONE;
        } else if (cpu_vendor == CPUVENDOR_AMD) {
@@ -239,6 +249,15 @@
                        wrmsr(MSR_IA32_SPEC_CTRL, 0);
                }
                break;
+       case V2_MITIGATION_INTEL_ENHANCED_IBRS:
+               msr = rdmsr(MSR_IA32_SPEC_CTRL);
+               if (enabled) {
+                       msr |= IA32_SPEC_CTRL_IBRS;
+               } else {
+                       msr &= ~IA32_SPEC_CTRL_IBRS;
+               }
+               wrmsr(MSR_IA32_SPEC_CTRL, msr);
+               break;
        case V2_MITIGATION_AMD_DIS_IND:
                msr = rdmsr(MSR_IC_CFG);
                if (enabled) {
@@ -302,6 +321,7 @@
                return EOPNOTSUPP;
        case V2_MITIGATION_AMD_DIS_IND:
        case V2_MITIGATION_INTEL_IBRS:
+       case V2_MITIGATION_INTEL_ENHANCED_IBRS:
                /* Initialize the barriers */
                ibrs_cpu_barrier1 = ncpu;
                ibrs_cpu_barrier2 = ncpu;