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[src/trunk]: src/sys/dev/pci KNF. No functional change.
details: https://anonhg.NetBSD.org/src/rev/b7895dd97005
branches: trunk
changeset: 456122:b7895dd97005
user: msaitoh <msaitoh%NetBSD.org@localhost>
date: Wed Apr 24 10:21:22 2019 +0000
description:
KNF. No functional change.
diffstat:
sys/dev/pci/if_wm.c | 248 +++++++++++++++++++++++----------------------------
1 files changed, 111 insertions(+), 137 deletions(-)
diffs (truncated from 790 to 300 lines):
diff -r b7bcc3752448 -r b7895dd97005 sys/dev/pci/if_wm.c
--- a/sys/dev/pci/if_wm.c Wed Apr 24 10:20:36 2019 +0000
+++ b/sys/dev/pci/if_wm.c Wed Apr 24 10:21:22 2019 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: if_wm.c,v 1.632 2019/03/25 05:32:01 msaitoh Exp $ */
+/* $NetBSD: if_wm.c,v 1.633 2019/04/24 10:21:22 msaitoh Exp $ */
/*
* Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
@@ -82,7 +82,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.632 2019/03/25 05:32:01 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.633 2019/04/24 10:21:22 msaitoh Exp $");
#ifdef _KERNEL_OPT
#include "opt_net_mpsafe.h"
@@ -546,10 +546,10 @@
int sc_nqueues;
struct wm_queue *sc_queue;
- u_int sc_tx_process_limit; /* Tx processing repeat limit in softint */
- u_int sc_tx_intr_process_limit; /* Tx processing repeat limit in H/W intr */
- u_int sc_rx_process_limit; /* Rx processing repeat limit in softint */
- u_int sc_rx_intr_process_limit; /* Rx processing repeat limit in H/W intr */
+ u_int sc_tx_process_limit; /* Tx proc. repeat limit in softint */
+ u_int sc_tx_intr_process_limit; /* Tx proc. repeat limit in H/W intr */
+ u_int sc_rx_process_limit; /* Rx proc. repeat limit in softint */
+ u_int sc_rx_intr_process_limit; /* Rx proc. repeat limit in H/W intr */
int sc_affinity_offset;
@@ -603,9 +603,12 @@
struct wm_nvmop nvm;
};
-#define WM_CORE_LOCK(_sc) if ((_sc)->sc_core_lock) mutex_enter((_sc)->sc_core_lock)
-#define WM_CORE_UNLOCK(_sc) if ((_sc)->sc_core_lock) mutex_exit((_sc)->sc_core_lock)
-#define WM_CORE_LOCKED(_sc) (!(_sc)->sc_core_lock || mutex_owned((_sc)->sc_core_lock))
+#define WM_CORE_LOCK(_sc) \
+ if ((_sc)->sc_core_lock) mutex_enter((_sc)->sc_core_lock)
+#define WM_CORE_UNLOCK(_sc) \
+ if ((_sc)->sc_core_lock) mutex_exit((_sc)->sc_core_lock)
+#define WM_CORE_LOCKED(_sc) \
+ (!(_sc)->sc_core_lock || mutex_owned((_sc)->sc_core_lock))
#define WM_RXCHAIN_RESET(rxq) \
do { \
@@ -641,7 +644,7 @@
#define CSR_WRITE(sc, reg, val) \
bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
#define CSR_WRITE_FLUSH(sc) \
- (void) CSR_READ((sc), WMREG_STATUS)
+ (void)CSR_READ((sc), WMREG_STATUS)
#define ICH8_FLASH_READ32(sc, reg) \
bus_space_read_4((sc)->sc_flasht, (sc)->sc_flashh, \
@@ -1924,7 +1927,7 @@
preg &= ~PCI_COMMAND_INVALIDATE_ENABLE;
pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, preg);
- /* power up chip */
+ /* Power up chip */
if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, NULL))
&& error != EOPNOTSUPP) {
aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error);
@@ -1984,7 +1987,7 @@
goto alloc_retry;
}
} else if (pci_intr_type(pc, sc->sc_intrs[0]) == PCI_INTR_TYPE_MSI) {
- wm_adjust_qnum(sc, 0); /* must not use multiqueue */
+ wm_adjust_qnum(sc, 0); /* Must not use multiqueue */
error = wm_setup_legacy(sc);
if (error) {
pci_intr_release(sc->sc_pc, sc->sc_intrs,
@@ -1996,7 +1999,7 @@
goto alloc_retry;
}
} else {
- wm_adjust_qnum(sc, 0); /* must not use multiqueue */
+ wm_adjust_qnum(sc, 0); /* Must not use multiqueue */
error = wm_setup_legacy(sc);
if (error) {
pci_intr_release(sc->sc_pc, sc->sc_intrs,
@@ -2304,7 +2307,7 @@
* NVM_SIZE_MULTIPLIER;
/* It is size in bytes, we want words */
sc->sc_nvm_wordsize /= 2;
- /* assume 2 banks */
+ /* Assume 2 banks */
sc->sc_ich8_flash_bank_size = sc->sc_nvm_wordsize / 2;
sc->sc_flashreg_offset = WM_PCH_SPT_FLASHOFFSET;
sc->phy.acquire = wm_get_swflag_ich8lan;
@@ -2583,7 +2586,7 @@
sc->sc_flags &= ~WM_F_WOL;
break;
case PCI_PRODUCT_INTEL_82546GB_QUAD_COPPER_KSP3:
- /* if quad port adapter, disable WoL on all but port A */
+ /* If quad port adapter, disable WoL on all but port A */
if (sc->sc_funcid != 0)
sc->sc_flags &= ~WM_F_WOL;
break;
@@ -2596,7 +2599,7 @@
case PCI_PRODUCT_INTEL_82571EB_QUAD_COPPER:
case PCI_PRODUCT_INTEL_82571EB_QUAD_FIBER:
case PCI_PRODUCT_INTEL_82571GB_QUAD_COPPER:
- /* if quad port adapter, disable WoL on all but port A */
+ /* If quad port adapter, disable WoL on all but port A */
if (sc->sc_funcid != 0)
sc->sc_flags &= ~WM_F_WOL;
break;
@@ -3134,11 +3137,9 @@
wm_watchdog_txq(ifp, txq, &hang_queue);
}
- /*
- * IF any of queues hanged up, reset the interface.
- */
+ /* IF any of queues hanged up, reset the interface. */
if (hang_queue != 0) {
- (void) wm_init(ifp);
+ (void)wm_init(ifp);
/*
* There are still some upper layer processing which call
@@ -3156,9 +3157,9 @@
mutex_enter(txq->txq_lock);
if (txq->txq_sending &&
- time_uptime - txq->txq_lastsent > wm_watchdog_timeout) {
+ time_uptime - txq->txq_lastsent > wm_watchdog_timeout)
wm_watchdog_txq_locked(ifp, txq, hang);
- }
+
mutex_exit(txq->txq_lock);
}
@@ -3196,28 +3197,28 @@
#ifdef WM_DEBUG
for (i = txq->txq_sdirty; i != txq->txq_snext;
i = WM_NEXTTXS(txq, i)) {
- txs = &txq->txq_soft[i];
- printf("txs %d tx %d -> %d\n",
- i, txs->txs_firstdesc, txs->txs_lastdesc);
- for (j = txs->txs_firstdesc; ; j = WM_NEXTTX(txq, j)) {
- if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
- printf("\tdesc %d: 0x%" PRIx64 "\n", j,
- txq->txq_nq_descs[j].nqtx_data.nqtxd_addr);
- printf("\t %#08x%08x\n",
- txq->txq_nq_descs[j].nqtx_data.nqtxd_fields,
- txq->txq_nq_descs[j].nqtx_data.nqtxd_cmdlen);
- } else {
- printf("\tdesc %d: 0x%" PRIx64 "\n", j,
- (uint64_t)txq->txq_descs[j].wtx_addr.wa_high << 32 |
- txq->txq_descs[j].wtx_addr.wa_low);
- printf("\t %#04x%02x%02x%08x\n",
- txq->txq_descs[j].wtx_fields.wtxu_vlan,
- txq->txq_descs[j].wtx_fields.wtxu_options,
- txq->txq_descs[j].wtx_fields.wtxu_status,
- txq->txq_descs[j].wtx_cmdlen);
- }
- if (j == txs->txs_lastdesc)
- break;
+ txs = &txq->txq_soft[i];
+ printf("txs %d tx %d -> %d\n",
+ i, txs->txs_firstdesc, txs->txs_lastdesc);
+ for (j = txs->txs_firstdesc; ; j = WM_NEXTTX(txq, j)) {
+ if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
+ printf("\tdesc %d: 0x%" PRIx64 "\n", j,
+ txq->txq_nq_descs[j].nqtx_data.nqtxd_addr);
+ printf("\t %#08x%08x\n",
+ txq->txq_nq_descs[j].nqtx_data.nqtxd_fields,
+ txq->txq_nq_descs[j].nqtx_data.nqtxd_cmdlen);
+ } else {
+ printf("\tdesc %d: 0x%" PRIx64 "\n", j,
+ (uint64_t)txq->txq_descs[j].wtx_addr.wa_high << 32 |
+ txq->txq_descs[j].wtx_addr.wa_low);
+ printf("\t %#04x%02x%02x%08x\n",
+ txq->txq_descs[j].wtx_fields.wtxu_vlan,
+ txq->txq_descs[j].wtx_fields.wtxu_options,
+ txq->txq_descs[j].wtx_fields.wtxu_status,
+ txq->txq_descs[j].wtx_cmdlen);
+ }
+ if (j == txs->txs_lastdesc)
+ break;
}
}
#endif
@@ -3352,7 +3353,7 @@
wm_ioctl(struct ifnet *ifp, u_long cmd, void *data)
{
struct wm_softc *sc = ifp->if_softc;
- struct ifreq *ifr = (struct ifreq *) data;
+ struct ifreq *ifr = (struct ifreq *)data;
struct ifaddr *ifa = (struct ifaddr *)data;
struct sockaddr_dl *sdl;
int s, error;
@@ -3394,7 +3395,7 @@
sdl = satosdl(ifp->if_dl->ifa_addr);
(void)sockaddr_dl_setaddr(sdl, sdl->sdl_len,
LLADDR(satosdl(ifa->ifa_addr)), ifp->if_addrlen);
- /* unicast address is first multicast entry */
+ /* Unicast address is the first multicast entry */
wm_set_filter(sc);
error = 0;
WM_CORE_UNLOCK(sc);
@@ -3622,11 +3623,11 @@
|| (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)
|| (sc->sc_type == WM_T_PCH_SPT) || (sc->sc_type == WM_T_PCH_CNP)){
hash = (enaddr[4] >> ich8_lo_shift[sc->sc_mchash_type]) |
- (((uint16_t) enaddr[5]) << ich8_hi_shift[sc->sc_mchash_type]);
+ (((uint16_t)enaddr[5]) << ich8_hi_shift[sc->sc_mchash_type]);
return (hash & 0x3ff);
}
hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) |
- (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]);
+ (((uint16_t)enaddr[5]) << hi_shift[sc->sc_mchash_type]);
return (hash & 0xfff);
}
@@ -3730,7 +3731,7 @@
ralmax = 1;
break;
default:
- /* available SHRA + RAR[0] */
+ /* Available SHRA + RAR[0] */
ralmax = i + 1;
}
} else
@@ -4518,7 +4519,7 @@
CSR_WRITE(sc, WMREG_RFCTL, reg);
break;
case WM_T_82574:
- /* use extened Rx descriptor. */
+ /* Use extened Rx descriptor. */
reg = CSR_READ(sc, WMREG_RFCTL);
reg |= WMREG_RFCTL_EXSTEN;
CSR_WRITE(sc, WMREG_RFCTL, reg);
@@ -4652,20 +4653,17 @@
delay(150);
reg = CSR_READ(sc, WMREG_RXDCTL(0));
- /* zero the lower 14 bits (prefetch and host thresholds) */
+ /* Zero the lower 14 bits (prefetch and host thresholds) */
reg &= 0xffffc000;
/*
- * update thresholds: prefetch threshold to 31, host threshold
+ * Update thresholds: prefetch threshold to 31, host threshold
* to 1 and make sure the granularity is "descriptors" and not
* "cache lines"
*/
reg |= (0x1f | (1 << 8) | RXDCTL_GRAN);
CSR_WRITE(sc, WMREG_RXDCTL(0), reg);
- /*
- * momentarily enable the RX ring for the changes to take
- * effect
- */
+ /* Momentarily enable the RX ring for the changes to take effect */
CSR_WRITE(sc, WMREG_RCTL, rctl | RCTL_EN);
CSR_WRITE_FLUSH(sc);
delay(150);
@@ -4947,7 +4945,7 @@
if (phy_reset != 0)
wm_get_cfg_done(sc);
- /* reload EEPROM */
+ /* Reload EEPROM */
switch (sc->sc_type) {
case WM_T_82542_2_0:
case WM_T_82542_2_1:
@@ -5044,7 +5042,7 @@
if ((sc->sc_type == WM_T_82580)
|| (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I354)) {
- /* clear global device reset status bit */
+ /* Clear global device reset status bit */
CSR_WRITE(sc, WMREG_STATUS, STATUS_DEV_RST_SET);
}
@@ -5068,7 +5066,7 @@
CSR_WRITE(sc, WMREG_KABGTXD, reg);
}
- /* reload sc_ctrl */
+ /* Reload sc_ctrl */
sc->sc_ctrl = CSR_READ(sc, WMREG_CTRL);
wm_set_eee(sc);
@@ -5093,7 +5091,7 @@
wm_pll_workaround_i210(sc);
if (sc->sc_type == WM_T_80003) {
- /* default to TRUE to enable the MDIC W/A */
+ /* Default to TRUE to enable the MDIC W/A */
sc->sc_flags |= WM_F_80003_MDIC_WA;
rv = wm_kmrn_readreg(sc,
@@ -5481,9 +5479,7 @@
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