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[src/trunk]: src/external/gpl3/gcc/dist/gcc revert local changes to riscv tha...
details: https://anonhg.NetBSD.org/src/rev/96c2f0d426bb
branches: trunk
changeset: 448353:96c2f0d426bb
user: mrg <mrg%NetBSD.org@localhost>
date: Thu Jan 31 06:46:16 2019 +0000
description:
revert local changes to riscv that come from the early gcc 4.8 era
patch for riscv that is now obsolete.
leave netbsd.h in place in case it is useful for the next re-porter.
diffstat:
external/gpl3/gcc/dist/gcc/common/config/riscv/riscv-common.c | 90 +-
external/gpl3/gcc/dist/gcc/config/riscv/constraints.md | 54 +-
external/gpl3/gcc/dist/gcc/config/riscv/default-32.h | 22 -
external/gpl3/gcc/dist/gcc/config/riscv/elf.h | 12 +-
external/gpl3/gcc/dist/gcc/config/riscv/linux-unwind.h | 50 -
external/gpl3/gcc/dist/gcc/config/riscv/linux.h | 59 +-
external/gpl3/gcc/dist/gcc/config/riscv/linux64.h | 43 -
external/gpl3/gcc/dist/gcc/config/riscv/opcode-riscv.h | 149 -
external/gpl3/gcc/dist/gcc/config/riscv/peephole.md | 134 +-
external/gpl3/gcc/dist/gcc/config/riscv/riscv-protos.h | 57 +-
external/gpl3/gcc/dist/gcc/config/riscv/riscv.c | 3636 ++++-----
external/gpl3/gcc/dist/gcc/config/riscv/riscv.h | 566 +-
external/gpl3/gcc/dist/gcc/config/riscv/riscv.md | 1535 +--
external/gpl3/gcc/dist/gcc/config/riscv/riscv.opt | 116 +-
external/gpl3/gcc/dist/gcc/config/riscv/sync.md | 54 +-
15 files changed, 2769 insertions(+), 3808 deletions(-)
diffs (truncated from 9278 to 300 lines):
diff -r 0bacd6df8af7 -r 96c2f0d426bb external/gpl3/gcc/dist/gcc/common/config/riscv/riscv-common.c
--- a/external/gpl3/gcc/dist/gcc/common/config/riscv/riscv-common.c Thu Jan 31 05:48:32 2019 +0000
+++ b/external/gpl3/gcc/dist/gcc/common/config/riscv/riscv-common.c Thu Jan 31 06:46:16 2019 +0000
@@ -1,5 +1,5 @@
/* Common hooks for RISC-V.
- Copyright (C) 1989-2014 Free Software Foundation, Inc.
+ Copyright (C) 2016 Free Software Foundation, Inc.
This file is part of GCC.
@@ -25,80 +25,87 @@
#include "common/common-target-def.h"
#include "opts.h"
#include "flags.h"
-#include "errors.h"
+#include "diagnostic-core.h"
/* Parse a RISC-V ISA string into an option mask. */
static void
-riscv_parse_arch_string (const char *isa, int *flags)
+riscv_parse_arch_string (const char *isa, int *flags, location_t loc)
{
const char *p = isa;
- if (strncmp (p, "RV32", 4) == 0)
- *flags |= MASK_32BIT, p += 4;
- else if (strncmp (p, "RV64", 4) == 0)
- *flags &= ~MASK_32BIT, p += 4;
-
- if (*p++ != 'I')
+ if (strncmp (p, "rv32", 4) == 0)
+ *flags &= ~MASK_64BIT, p += 4;
+ else if (strncmp (p, "rv64", 4) == 0)
+ *flags |= MASK_64BIT, p += 4;
+ else
{
- error ("-march=%s: ISA strings must begin with I, RV32I, or RV64I", isa);
+ error_at (loc, "-march=%s: ISA string must begin with rv32 or rv64", isa);
return;
}
- *flags &= ~MASK_MULDIV;
- if (*p == 'M')
- *flags |= MASK_MULDIV, p++;
+ if (*p == 'g')
+ {
+ p++;
- *flags &= ~MASK_ATOMIC;
- if (*p == 'A')
- *flags |= MASK_ATOMIC, p++;
-
- *flags |= MASK_SOFT_FLOAT_ABI;
- if (*p == 'F')
- *flags &= ~MASK_SOFT_FLOAT_ABI, p++;
-
- if (*p == 'D')
+ *flags |= MASK_MUL;
+ *flags |= MASK_ATOMIC;
+ *flags |= MASK_HARD_FLOAT;
+ *flags |= MASK_DOUBLE_FLOAT;
+ }
+ else if (*p == 'i')
{
p++;
- if (!TARGET_HARD_FLOAT)
+
+ *flags &= ~MASK_MUL;
+ if (*p == 'm')
+ *flags |= MASK_MUL, p++;
+
+ *flags &= ~MASK_ATOMIC;
+ if (*p == 'a')
+ *flags |= MASK_ATOMIC, p++;
+
+ *flags &= ~(MASK_HARD_FLOAT | MASK_DOUBLE_FLOAT);
+ if (*p == 'f')
{
- error ("-march=%s: the D extension requires the F extension", isa);
- return;
+ *flags |= MASK_HARD_FLOAT, p++;
+
+ if (*p == 'd')
+ {
+ *flags |= MASK_DOUBLE_FLOAT;
+ p++;
+ }
}
}
- else if (TARGET_HARD_FLOAT)
+ else
{
- error ("-march=%s: single-precision-only is not yet supported", isa);
+ error_at (loc, "-march=%s: invalid ISA string", isa);
return;
}
+ *flags &= ~MASK_RVC;
+ if (*p == 'c')
+ *flags |= MASK_RVC, p++;
+
if (*p)
{
- error ("-march=%s: unsupported ISA substring %s", isa, p);
+ error_at (loc, "-march=%s: unsupported ISA substring %qs", isa, p);
return;
}
}
-static int
-riscv_flags_from_arch_string (const char *isa)
-{
- int flags = 0;
- riscv_parse_arch_string (isa, &flags);
- return flags;
-}
-
/* Implement TARGET_HANDLE_OPTION. */
static bool
riscv_handle_option (struct gcc_options *opts,
struct gcc_options *opts_set ATTRIBUTE_UNUSED,
const struct cl_decoded_option *decoded,
- location_t loc ATTRIBUTE_UNUSED)
+ location_t loc)
{
switch (decoded->opt_index)
{
case OPT_march_:
- riscv_parse_arch_string (decoded->arg, &opts->x_target_flags);
+ riscv_parse_arch_string (decoded->arg, &opts->x_target_flags, loc);
return true;
default:
@@ -111,18 +118,13 @@
{
{ OPT_LEVELS_1_PLUS, OPT_fsection_anchors, NULL, 1 },
{ OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
+ { OPT_LEVELS_2_PLUS, OPT_free, NULL, 1 },
{ OPT_LEVELS_NONE, 0, NULL, 0 }
};
#undef TARGET_OPTION_OPTIMIZATION_TABLE
#define TARGET_OPTION_OPTIMIZATION_TABLE riscv_option_optimization_table
-#undef TARGET_DEFAULT_TARGET_FLAGS
-#define TARGET_DEFAULT_TARGET_FLAGS \
- (TARGET_DEFAULT \
- | riscv_flags_from_arch_string (RISCV_ARCH_STRING_DEFAULT) \
- | (TARGET_64BIT_DEFAULT ? 0 : MASK_32BIT))
-
#undef TARGET_HANDLE_OPTION
#define TARGET_HANDLE_OPTION riscv_handle_option
diff -r 0bacd6df8af7 -r 96c2f0d426bb external/gpl3/gcc/dist/gcc/config/riscv/constraints.md
--- a/external/gpl3/gcc/dist/gcc/config/riscv/constraints.md Thu Jan 31 05:48:32 2019 +0000
+++ b/external/gpl3/gcc/dist/gcc/config/riscv/constraints.md Thu Jan 31 06:46:16 2019 +0000
@@ -1,6 +1,6 @@
;; Constraint definitions for RISC-V target.
-;; Copyright (C) 2011-2014 Free Software Foundation, Inc.
-;; Contributed by Andrew Waterman (waterman%cs.berkeley.edu@localhost) at UC Berkeley.
+;; Copyright (C) 2011-2017 Free Software Foundation, Inc.
+;; Contributed by Andrew Waterman (andrew%sifive.com@localhost).
;; Based on MIPS target for GNU compiler.
;;
;; This file is part of GCC.
@@ -24,18 +24,15 @@
(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : NO_REGS"
"A floating-point register (if available).")
-(define_register_constraint "b" "ALL_REGS"
- "@internal")
-
-(define_register_constraint "j" "T_REGS"
+(define_register_constraint "j" "SIBCALL_REGS"
"@internal")
-;; Integer constraints
+;; Avoid using register t0 for JALR's argument, because for some
+;; microarchitectures that is a return-address stack hint.
+(define_register_constraint "l" "JALR_REGS"
+ "@internal")
-(define_constraint "Z"
- "@internal"
- (and (match_code "const_int")
- (match_test "1")))
+;; General constraints
(define_constraint "I"
"An I-type 12-bit signed immediate."
@@ -47,19 +44,18 @@
(and (match_code "const_int")
(match_test "ival == 0")))
-;; Floating-point constraints
+(define_constraint "K"
+ "A 5-bit unsigned immediate for CSR access instructions."
+ (and (match_code "const_int")
+ (match_test "IN_RANGE (ival, 0, 31)")))
+;; Floating-point constant +0.0, used for FCVT-based moves when FMV is
+;; not available in RV32.
(define_constraint "G"
- "Floating-point zero."
+ "@internal"
(and (match_code "const_double")
(match_test "op == CONST0_RTX (mode)")))
-;; General constraints
-
-(define_constraint "Q"
- "@internal"
- (match_operand 0 "const_arith_operand"))
-
(define_memory_constraint "A"
"An address that is held in a general-purpose register."
(and (match_code "mem")
@@ -68,23 +64,15 @@
(define_constraint "S"
"@internal
A constant call address."
- (and (match_operand 0 "call_insn_operand")
- (match_test "CONSTANT_P (op)")))
+ (match_operand 0 "absolute_symbolic_operand"))
+
+(define_constraint "U"
+ "@internal
+ A PLT-indirect call address."
+ (match_operand 0 "plt_symbolic_operand"))
(define_constraint "T"
"@internal
A constant @code{move_operand}."
(and (match_operand 0 "move_operand")
(match_test "CONSTANT_P (op)")))
-
-(define_memory_constraint "W"
- "@internal
- A memory address based on a member of @code{BASE_REG_CLASS}."
- (and (match_code "mem")
- (match_operand 0 "memory_operand")))
-
-(define_constraint "YG"
- "@internal
- A vector zero."
- (and (match_code "const_vector")
- (match_test "op == CONST0_RTX (mode)")))
diff -r 0bacd6df8af7 -r 96c2f0d426bb external/gpl3/gcc/dist/gcc/config/riscv/default-32.h
--- a/external/gpl3/gcc/dist/gcc/config/riscv/default-32.h Thu Jan 31 05:48:32 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,22 +0,0 @@
-/* Definitions of target machine for GCC, for RISC-V,
- defaulting to 32-bit code generation.
-
- Copyright (C) 1999-2014 Free Software Foundation, Inc.
-
-This file is part of GCC.
-
-GCC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 3, or (at your option)
-any later version.
-
-GCC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GCC; see the file COPYING3. If not see
-<http://www.gnu.org/licenses/>. */
-
-#define TARGET_64BIT_DEFAULT 0
diff -r 0bacd6df8af7 -r 96c2f0d426bb external/gpl3/gcc/dist/gcc/config/riscv/elf.h
--- a/external/gpl3/gcc/dist/gcc/config/riscv/elf.h Thu Jan 31 05:48:32 2019 +0000
+++ b/external/gpl3/gcc/dist/gcc/config/riscv/elf.h Thu Jan 31 06:46:16 2019 +0000
@@ -1,6 +1,5 @@
/* Target macros for riscv*-elf targets.
- Copyright (C) 1994, 1997, 1999, 2000, 2002, 2003, 2004, 2007, 2010
- Free Software Foundation, Inc.
+ Copyright (C) 1994-2017 Free Software Foundation, Inc.
This file is part of GCC.
@@ -18,9 +17,14 @@
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
-/* Leave the linker script to choose the appropriate libraries. */
+#define LINK_SPEC "\
+-melf" XLEN_SPEC "lriscv \
+%{shared}"
+
+/* Link against Newlib libraries, because the ELF backend assumes Newlib.
+ Handle the circular dependence between libc and libgloss. */
#undef LIB_SPEC
-#define LIB_SPEC ""
+#define LIB_SPEC "--start-group -lc -lgloss --end-group"
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